Ponencia
Implementation of a time-warping AER mapper
Autor/es | Linares Barranco, Alejandro
Gómez Rodríguez, Francisco de Asís Jiménez Moreno, Gabriel Delbruck, Tobias Berner, Raphael Liu, Shih-Chii |
Departamento | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores |
Fecha de publicación | 2009 |
Fecha de depósito | 2019-12-27 |
Publicado en |
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ISBN/ISSN | 978-1-4244-3827-3 0271-4302 |
Resumen | In recent implementations of neuromorphic spikebased
sensors, multi-neuron processors, and actuators; the spike
traffic between devices is coded in the form of asynchronous
spike streams following the Address-Event-Re ... In recent implementations of neuromorphic spikebased sensors, multi-neuron processors, and actuators; the spike traffic between devices is coded in the form of asynchronous spike streams following the Address-Event-Representation protocol. This spike information can be modified during the transmission from one device to another by using a mapper device. In this paper we present a mapper implementation which transforms event addresses and can also delay events in time. We discuss two different architectures for implementing the time delays on an FPGA board (USB-AER), and we present an example of the use of the time delay feature in the mapper in an implementation of a visual elementary motion detection model based on the spike outputs of a temporal contrast retina. |
Identificador del proyecto | TEC2006-11730-C03-02
P06-TIC-01417 |
Cita | Linares Barranco, A., Gómez Rodríguez, F.d.A., Jiménez Moreno, G., Delbruck, T., Berner, R. y Liu, S.C. (2009). Implementation of a time-warping AER mapper. En ISCAS 2009: IEEE International Symposium on Circuits and Systems (2886-2889), Taipei, Taiwan: IEEE Computer Society. |
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