A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach
|Author/s||Jiménez Fernández, Ángel Francisco
Cerezuela Escudero, Elena
Miró Amarante, María Lourdes
Domínguez Morales, Manuel Jesús
Gómez Rodríguez, Francisco de Asís
Linares Barranco, Alejandro
Jiménez Moreno, Gabriel
|Department||Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores|
|Abstract||This paper presents a new architecture, design
flow, and field-programmable gate array (FPGA) implementation
analysis of a neuromorphic binaural auditory sensor, designed
completely in the spike domain. Unlike digital ...
This paper presents a new architecture, design flow, and field-programmable gate array (FPGA) implementation analysis of a neuromorphic binaural auditory sensor, designed completely in the spike domain. Unlike digital cochleae that decompose audio signals using classical digital signal processing techniques, the model presented in this paper processes information directly encoded as spikes using pulse frequency modulation and provides a set of frequency-decomposed audio information using an address-event representation interface. In this case, a systematic approach to design led to a generic process for building, tuning, and implementing audio frequency decomposers with different features, facilitating synthesis with custom features. This allows researchers to implement their own parameterized neuromorphic auditory systems in a low-cost FPGA in order to study the audio processing and learning activity that takes place in the brain. In this paper, we present a 64-channel binaural neuromorphic auditory system implemented in a Virtex-5 FPGA using a commercial development board. The system was excited with a diverse set of audio signals in order to analyze its response and characterize its features. The neuromorphic auditory system response times and frequencies are reported. The experimental results of the proposed system implementation with 64-channel stereo are: a frequency range between 9.6 Hz and 14.6 kHz (adjustable), a maximum output event rate of 2.19 Mevents/s, a power consumption of 29.7 mW, the slices requirements of 11 141, and a system clock frequency of 27 MHz.
|Citation||Jiménez Fernández, Á.F., Cerezuela Escudero, E., Miró Amarante, M.L., Domínguez Morales, M.J., Gómez Rodríguez, F.d.A., Linares Barranco, A. y Jiménez Moreno, G. (2017). A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach. IEEE Transactions on Neural Networks and Learning Systems, 28 (4), 804-818.|
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