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Mostrando ítems 1-10 de 11
Artículo
nu MOS-based sorter for arithmetic applications
(Hindawi Publishing Corporation, 2000)
The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an (8×8)-multiplier and a (15,4) counter which use a ...
Artículo
SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips
(Wiley-Blackwell, 1999)
This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of ...
Artículo
Multiplexing architecture for mixed-signal CMOS fuzzy controllers
(Institute of Electrical and Electronics Engineers, 1998)
Limited precision imposes limits on the complexity of analogue circuits, and hence fuzzy analogue controllers are usually oriented to fast low-power systems with low-medium complexity. A strategy to preserve most of the ...
Artículo
A modular programmable CMOS analog fuzzy controller chip
(Institute of Electrical and Electronics Engineers, 1999)
We present a highly modular fuzzy inference analog CMOS chip architecture with on-chip digital progranirnability. This chip consists of the interconnection of parameterized instances of two different kind of blocks, namely ...
Artículo
1 V CMOS subthreshold log domain PDM
(Springer, 2003)
A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing ...
Artículo
Efficient realization of a threshold voter for self-purging redundancy
(Springer, 2001)
The self-purging technique is not commonly used mainly due to the lack of practical implementations of its key component, the threshold voter. A very efficient implementation of this voter is presented which uses a ...
Artículo
A CMOS 0.8- µm transistor-only 1.63-MHz switched-current bandpass ΣΔ modulator for AM signal A/D conversion
(Institute of Electrical and Electronics Engineers, 2000)
This paper presents a CMOS 0.8-/spl mu/m switched-current (SI) fourth-order bandpass /spl Sigma//spl Delta/ modulator (BP-/spl Sigma//spl Delta/M) IC capable of handling signals up to 1.63 MHz with 105-bit resolution and ...
Artículo
Sorting networks implemented as νMOS circuits
(Institute of Electrical and Electronics Engineers, 1998)
A new realisation for n-input sorters is presented. Resorting to the neuron-MOS (νMOS) concept and to an adequate electrical scheme, a compact and efficient implementation is obtained.
Artículo
Low-voltage CMOS log-companding techniques for audio applications
(Springer, 2004)
This paper presents a collection of novel current-mode circuit techniques for the integration of very low-voltage (down to 1 V) low-power (few hundreds of μA) complete SoCs in CMOS technologies. The new design proposal is ...
Artículo
Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors
(Institute of Electrical and Electronics Engineers, 1998)
This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a cascade architecture to obtain high resolution with low oversampling ratio. It is less sensitive to the non-linearity of ...