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Assessing application areas for tunnel transistor technologies [Presentation]
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this ...
Complementary tunnel gate topology to reduce crosstalk effects [Presentation]
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges ...
Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas [Article]
(Institute of Electrical and Electronics Engineers, 2016)
In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than ...