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Mostrando ítems 1-7 de 7
Ponencia
Automated experimental setup for EM cartography to enhance EM attacks
(2022)
Side-channel attacks are a real threat, exploiting and revealing the secret data stored in our electronic devices just analyzing the leaked information of the cryptographic modules during their normal encryption/decryption ...
Ponencia
Using physical unclonable functions for hardware authentication: a survey
(2010)
Physical unclonable functions (PUFs) are drawing a crescent interest in hardware oriented security due to their special characteristics of simplicity and safety. However, their nature as well as early stage of study makes ...
Ponencia
Asymmetric clock driver for improved power and noise performances
(IEEE Computer Society, 2007)
One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation and distribution tree. This paper analyzes how the use of an asymmetric clock can be an ...
Ponencia
ASIC-in-the-loop methodology for verification of piecewise affine controllers
(Institute of Electrical and Electronics Engineers, 2012)
This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable application specific integrated circuit (ASIC) that imple- ments piecewise affine (PWA) controllers. ...
Ponencia
Gate-Level Simulation of CMOS Circuits Using the IDDM Model
(IEEE Computer Society, 2001)
Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is ...
Ponencia
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
(IEEE Computer Society, 2001)
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm ...
Ponencia
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters
(Springer, 2002)
The objective of this paper is to explore the applicability of clock gating techniques to binary counters in order to reduce the power consumption as well as the switching noise generation. A measurement methodology to ...