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dc.contributor.editorMaloberti, Francoes
dc.contributor.editorSetti, Gianlucaes
dc.creatorYousefzadeh, Amirrezaes
dc.creatorOrchard, Garrickes
dc.creatorStromatias, Evangeloses
dc.creatorSerrano Gotarredona, María Teresaes
dc.creatorLinares Barranco, Bernabées
dc.date.accessioned2020-07-08T07:51:09Z
dc.date.available2020-07-08T07:51:09Z
dc.date.issued2018
dc.identifier.issn0271-4310es
dc.identifier.issn2379-447Xes
dc.identifier.urihttps://hdl.handle.net/11441/98971
dc.description.abstractInterest in event-based vision sensors has proliferated in recent years, with innovative technology becoming more accessible to new researchers and highlighting such sensors’ potential to enable low-latency sensing at low computational cost. These sensors can outperform frame-based vision sensors regarding data compression, dynamic range, temporal resolution and power efficiency. However, available mature framebased processing methods by using Artificial Neural Networks (ANNs) surpass Spiking Neural Networks (SNNs) in terms of accuracy of recognition. In this paper, we introduce a Hybrid Neural Network which is an intermediate solution to exploit advantages of both event-based and frame-based processing.We have implemented this network in FPGA and benchmarked its performance by using different event-based versions of MNIST dataset. HDL codes for this project are available for academic purpose upon request.es
dc.formatapplication/pdfes
dc.format.extent15 p.es
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)es
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectVoltage controles
dc.subjectNeuronses
dc.subjectBiological neural networkses
dc.subjectField programmable gate arrayses
dc.subjectHardwarees
dc.subjectSensorses
dc.titleHybrid Neural Network, An Efficient Low-Power Digital Hardware Implementation of Event-based Artificial Neural Networkes
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessrightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadoreses
dc.relation.publisherversionhttps://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8351562&isnumber=8350884es
dc.identifier.doi10.1109/ISCAS.2018.8351562es
dc.contributor.groupUniversidad de Sevilla. TIC178: Diseño y Test de Circuitos Integrados de Señal Mixtaes
idus.validador.notaPostprintes
dc.eventtitleISCAS2018. IEEE International Symposium on Circuits and Systemses
dc.eventinstitutionFlorence (Italy)es

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Attribution-NonCommercial-NoDerivatives 4.0 Internacional
Except where otherwise noted, this item's license is described as: Attribution-NonCommercial-NoDerivatives 4.0 Internacional