dc.creator | Liñán Cembrano, Gustavo | es |
dc.creator | Domínguez Castro, Rafael | es |
dc.creator | Espejo Meana, Servando Carlos | es |
dc.creator | Roca Moreno, Elisenda | es |
dc.creator | Foldesy, Péter | es |
dc.creator | Rodríguez Vázquez, Ángel Benito | es |
dc.date.accessioned | 2020-04-29T14:47:53Z | |
dc.date.available | 2020-04-29T14:47:53Z | |
dc.date.issued | 2000 | |
dc.identifier.citation | Liñán Cembrano, G., Domínguez Castro, R., Espejo Meana, S.C., Roca Moreno, E., Foldesy, P. y Rodríguez Vázquez, Á.B. (2000). Experimental demonstration of real-time image-processing using a VLSI analog programmable array processor. En Applications of Artificial Neural Networks in Image Processing V (235-246), San Jose, USA: SPIE- The International Society for Optical Engineering. | |
dc.identifier.issn | 0277-786X | es |
dc.identifier.issn | 1996-756X | es |
dc.identifier.uri | https://hdl.handle.net/11441/95978 | |
dc.description.abstract | This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitallyprogrammable
analog parallel processing, and distributed image memory —cache— on a common silicon substrate. This chip,
designed in a O.5ptm CMOS standard technology contains around 1, 000, 000 transistors, 80% of which operate in analog
mode; it is hence one the most complex mixed-signal chip reported to now. Chip functional features are in accordance to the
CNN Universal Machine paradigm: cellular, spatial-invariant array architecture; programmable local interactions among
cells; randomly-selectable memory of instructions (elementary instructions are defined by specific values of the cell local
interactions); random storage/retrieval of intermediate images; capability to complete algorithmic image processing tasks
controlled by the user-selected stored instructions and interacting with the cache memory, etc. Thus, as illustrated in this
paper, the chip is capable to complete complex spatio-temporal image processing tasks within short computation time
( 200ns for linear convolutions) and using a low power budget (<1.2W for the complete chip). The internal circuitry of the
chip has been designed to operate in robust manner with >7-bit equivalent accuracy in the internal analog operations, which
has been confirmed by experimental measurements. Hence, to all practical purposes, processing tasks completed by the chip
have the same accuracy than those completed by digital processors preceded by 7-bit digital-to-analog converters for image
digitalization. Such 7-bit accuracy is enough for most image processing applications.
The paper briefly describes the chip architecture and focus mostly on presenting experimental evidences of the chip
functionality. Multiscale low-pass and high-pass filtering ofgray-scale images, analog edges extraction, image segmentation,
thresholded gradient detection, mathematical morphology operations, shortest path detection in a labyrinth, skeletonizing,
image reconstruction, several non-linear type image processing taks like absolute value calculation or gray-scale gradient
detection and real-time motion detection in QCIF video sequences are some of the very interesting applications that have
been demonstrated as available when using the prototype. | es |
dc.description.sponsorship | Office of Naval Research (USA) N68171-98-C-9004 | es |
dc.description.sponsorship | European Commission DICTAM IST-1999-19007, TIC 990826 | es |
dc.format | application/pdf | es |
dc.format.extent | 11 p. | es |
dc.language.iso | eng | es |
dc.publisher | SPIE- The International Society for Optical Engineering | es |
dc.relation.ispartof | Applications of Artificial Neural Networks in Image Processing V (2000), pp. 235-246. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Experimental demonstration of real-time image-processing using a VLSI analog programmable array processor | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | N68171-98-C-9004 | es |
dc.relation.projectID | DICTAM IST-1999-19007 | es |
dc.relation.projectID | TIC 990826 | es |
dc.relation.publisherversion | https://doi.org/10.1117/12.382917 | es |
dc.identifier.doi | 10.1117/12.382917 | es |
dc.publication.initialPage | 235 | es |
dc.publication.endPage | 246 | es |
dc.eventtitle | Applications of Artificial Neural Networks in Image Processing V | es |
dc.eventinstitution | San Jose, USA | es |
dc.identifier.sisius | 5602984 | es |