A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors

Domínguez Castro, Rafael; Espejo Meana, Servando Carlos; Rodríguez Vázquez, Ángel Benito; Carmona Galán, Ricardo

doi:10.1109/AMICD.1997.637203

Ponencia

dc.creator	Domínguez Castro, Rafael	es
dc.creator	Espejo Meana, Servando Carlos	es
dc.creator	Rodríguez Vázquez, Ángel Benito	es
dc.creator	Carmona Galán, Ricardo	es
dc.date.accessioned	2020-04-20T15:03:19Z
dc.date.available	2020-04-20T15:03:19Z
dc.date.issued	1997
dc.identifier.citation	Domínguez Castro, R., Espejo Meana, S.C., Rodríguez Vázquez, Á.B. y Carmona Galán, R. (1997). A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors. En 2nd IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design (117-122), Baveno, Italia: Institute of Electrical and Electronics Engineers.
dc.identifier.isbn	0-7803-4240-2	es
dc.identifier.uri	https://hdl.handle.net/11441/95484
dc.description.abstract	This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip.	es
dc.description.sponsorship	Comisión Interministerial de Ciencia y Tecnología TIC96- 1392-C02-02	es
dc.format	application/pdf	es
dc.format.extent	6 p.	es
dc.language.iso	eng	es
dc.publisher	Institute of Electrical and Electronics Engineers	es
dc.relation.ispartof	2nd IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design (1997), pp. 117-122.
dc.rights	Attribution-NonCommercial-NoDerivatives 4.0 Internacional	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/4.0/	*
dc.title	A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors	es
dc.type	info:eu-repo/semantics/conferenceObject	es
dcterms.identifier	https://ror.org/03yxnpp24
dc.type.version	info:eu-repo/semantics/acceptedVersion	es
dc.rights.accessRights	info:eu-repo/semantics/openAccess	es
dc.contributor.affiliation	Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo	es
dc.relation.projectID	TIC96- 1392-C02-02	es
dc.relation.publisherversion	https://doi.org/10.1109/AMICD.1997.637203	es
dc.identifier.doi	10.1109/AMICD.1997.637203	es
dc.publication.initialPage	117	es
dc.publication.endPage	122	es
dc.eventtitle	2nd IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design	es
dc.eventinstitution	Baveno, Italia	es
dc.identifier.sisius	5406224	es

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