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dc.creatorNúñez Martínez, Juanes
dc.creatorAvedillo de Juan, María Josées
dc.date.accessioned2020-04-14T10:08:23Z
dc.date.available2020-04-14T10:08:23Z
dc.date.issued2019-01
dc.identifier.citationNúñez Martínez, J. y Avedillo de Juan, M.J. (2019). Power and Speed Evaluation of Hyper-FET Circuits. IEEE Access, 7, 6724-6732.
dc.identifier.issn2169-3536es
dc.identifier.issn2169-3536es
dc.identifier.urihttps://hdl.handle.net/11441/95124
dc.description.abstractMany emerging devices are currently being explored as potential alternatives to complementary metal–oxide–semiconductor technologies for overcoming power density and energy efficiency limitations. It is now generally accepted that these emerging devices need to be evaluated at the circuit level. In this paper, we investigate the speed and power performance of hyper-field-effect transistor (Hyper-FET) circuits, comparing them with both high-performance and low standby power fin-shaped FET designs on the same technology node. The evaluation, which was carried out at the gate level and circuit level, includes a characterization of 8-bit ripple carry adders. Our experiments showed around 80% speed degradation and 30% power savings for a given range of operating frequencies. These power savings were much smaller than those predicted from the transistor- and gate-level estimations. Deviations from the ideal expected behavior of the Hyper-FET circuitry are illustrated, which support the obtained results.es
dc.description.sponsorshipMinisterio de Economía y Competitividad TEC2017-87052-Pes
dc.formatapplication/pdfes
dc.language.isoenges
dc.relation.ispartofIEEE Access, 7, 6724-6732.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectHyper-FETes
dc.subjectLow voltagees
dc.subjectLow poweres
dc.subjectPhase transition materialses
dc.subjectSteep subthreshold slopees
dc.titlePower and Speed Evaluation of Hyper-FET Circuitses
dc.typeinfo:eu-repo/semantics/articlees
dc.type.versioninfo:eu-repo/semantics/publishedVersiones
dc.rights.accessrightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDTEC2017-87052-Pes
dc.journaltitleIEEE Access
dc.publication.volumen7
dc.publication.initialPage6724
dc.publication.endPage6732
dc.contributor.funderMinisterio de Economía y Competitividad (MINECO). Españaes

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Attribution-NonCommercial-NoDerivatives 4.0 Internacional
Except where otherwise noted, this item's license is described as: Attribution-NonCommercial-NoDerivatives 4.0 Internacional