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Artículo
Power and Speed Evaluation of Hyper-FET Circuits
dc.creator | Núñez Martínez, Juan | es |
dc.creator | Avedillo de Juan, María José | es |
dc.date.accessioned | 2020-04-14T10:08:23Z | |
dc.date.available | 2020-04-14T10:08:23Z | |
dc.date.issued | 2019-01 | |
dc.identifier.citation | Núñez Martínez, J. y Avedillo de Juan, M.J. (2019). Power and Speed Evaluation of Hyper-FET Circuits. IEEE Access, 7, 6724-6732. | |
dc.identifier.issn | 2169-3536 | es |
dc.identifier.issn | 2169-3536 | es |
dc.identifier.uri | https://hdl.handle.net/11441/95124 | |
dc.description.abstract | Many emerging devices are currently being explored as potential alternatives to complementary metal–oxide–semiconductor technologies for overcoming power density and energy efficiency limitations. It is now generally accepted that these emerging devices need to be evaluated at the circuit level. In this paper, we investigate the speed and power performance of hyper-field-effect transistor (Hyper-FET) circuits, comparing them with both high-performance and low standby power fin-shaped FET designs on the same technology node. The evaluation, which was carried out at the gate level and circuit level, includes a characterization of 8-bit ripple carry adders. Our experiments showed around 80% speed degradation and 30% power savings for a given range of operating frequencies. These power savings were much smaller than those predicted from the transistor- and gate-level estimations. Deviations from the ideal expected behavior of the Hyper-FET circuitry are illustrated, which support the obtained results. | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2017-87052-P | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.relation.ispartof | IEEE Access, 7, 6724-6732. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Hyper-FET | es |
dc.subject | Low voltage | es |
dc.subject | Low power | es |
dc.subject | Phase transition materials | es |
dc.subject | Steep subthreshold slope | es |
dc.title | Power and Speed Evaluation of Hyper-FET Circuits | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TEC2017-87052-P | es |
dc.journaltitle | IEEE Access | |
dc.publication.volumen | 7 | |
dc.publication.initialPage | 6724 | |
dc.publication.endPage | 6732 | |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | es |
Ficheros | Tamaño | Formato | Ver | Descripción |
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10.1109_ACCESS.2018.2889016.pdf | 5.466Mb | [PDF] | Ver/ | |