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dc.creatorLinares Barranco, Alejandroes
dc.creatorGómez Rodríguez, Francisco de Asíses
dc.creatorJiménez Fernández, Ángel Franciscoes
dc.creatorDelbrück, T.es
dc.creatorLichtensteiner, P.es
dc.date.accessioned2020-01-30T11:51:04Z
dc.date.available2020-01-30T11:51:04Z
dc.date.issued2007
dc.identifier.citationLinares Barranco, A., Gómez Rodríguez, F.d.A., Jiménez Fernández, Á.F., Delbrück, T. y Lichtensteiner, P. (2007). Using FPGA for visuo-motor control with a silicon retina and a humanoid robot. En ISCAS 2007: IEEE International Symposium on Circuits and Systems (1192-1195), New Orleans, USA: IEEE Computer Society.
dc.identifier.isbn1-4244-0920-9es
dc.identifier.issn0271-4302es
dc.identifier.urihttps://hdl.handle.net/11441/92590
dc.description.abstractThe address-event representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI chips. The event information is transferred using a high speed digital parallel bus. This paper present an experiment based on AER for visual sensing, processing and finally actuating a robot. The AER output of a silicon retina is processed by an AER filter implemented into a FPGA to produce a mimicking behaviour in a humanoid robot (The RoboSapiens V2). We have implemented the visual filter into the Spartan II FPGA of the USB-AER platform and the Central Pattern Generator (CPG) into the Spartan 3 FPGA of the AER-Robot platform, both developed by authors.es
dc.description.sponsorshipUnión Europea IST-2001-34124 (CAVIAR)es
dc.description.sponsorshipMinisterio de Ciencia y Tecnología TIC-2003-08164-C03-02es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherIEEE Computer Societyes
dc.relation.ispartofISCAS 2007: IEEE International Symposium on Circuits and Systems (2007), p 1192-1195
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.titleUsing FPGA for visuo-motor control with a silicon retina and a humanoid robotes
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadoreses
dc.relation.projectIDIST-2001-34124 (CAVIAR)es
dc.relation.projectIDTIC-2003-08164-C03-02es
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/4252855es
dc.identifier.doi10.1109/ISCAS.2007.378265es
idus.format.extent4es
dc.publication.initialPage1192es
dc.publication.endPage1195es
dc.eventtitleISCAS 2007: IEEE International Symposium on Circuits and Systemses
dc.eventinstitutionNew Orleans, USAes
dc.relation.publicationplaceNew York, USAes

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