dc.creator | Ríos Navarro, José Antonio | es |
dc.creator | Tapiador Morales, Ricardo | es |
dc.creator | Jiménez Fernández, Ángel Francisco | es |
dc.creator | Domínguez Morales, Manuel Jesús | es |
dc.creator | Amaya Rodríguez, Claudio Antonio | es |
dc.creator | Linares Barranco, Alejandro | es |
dc.date.accessioned | 2020-01-29T08:50:20Z | |
dc.date.available | 2020-01-29T08:50:20Z | |
dc.date.issued | 2018 | |
dc.identifier.citation | Rios Navarro, A., Tapiador Morales, R., Jiménez Fernández, Á.F., Domínguez Morales, M.J., Amaya Rodríguez, C.A. y Linares Barranco, A. (2018). Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator. En IEEE-NANO 2018: 18th International Conference on Nanotechnology Cork, Ireland: IEEE Computer Society. | |
dc.identifier.isbn | 978-1-5386-5336-4 | es |
dc.identifier.issn | 1944-9380 | es |
dc.identifier.uri | https://hdl.handle.net/11441/92448 | |
dc.description.abstract | Many FPGAs vendors have recently included embedded
processors in their devices, like Xilinx with ARM-Cortex
A cores, together with programmable logic cells. These devices
are known as Programmable System on Chip (PSoC). Their ARM
cores (embedded in the processing system or PS) communicates
with the programmable logic cells (PL) using ARM-standard AXI
buses. In this paper we analyses the performance of exhaustive
data transfers between PS and PL for a Xilinx Zynq FPGA
in a co-design real scenario for Convolutional Neural Networks
(CNN) accelerator, which processes, in dedicated hardware, a
stream of visual information from a neuromorphic visual sensor
for classification. In the PS side, a Linux operating system is
running, which recollects visual events from the neuromorphic
sensor into a normalized frame, and then it transfers these
frames to the accelerator of multi-layered CNNs, and read results,
using an AXI-DMA bus in a per-layer way. As these kind of
accelerators try to process information as quick as possible, data
bandwidth becomes critical and maintaining a good balanced
data throughput rate requires some considerations. We present
and evaluate several data partitioning techniques to improve the
balance between RX and TX transfer and two different ways
of transfers management: through a polling routine at the userlevel
of the OS, and through a dedicated interrupt-based kernellevel
driver. We demonstrate that for longer enough packets,
the kernel-level driver solution gets better timing in computing a
CNN classification example. Main advantage of using kernel-level
driver is to have safer solutions and to have tasks scheduling in
the OS to manage other important processes for our application,
like frames collection from sensors and their normalization. | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2016-77785-P | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | IEEE-NANO 2018: 18th International Conference on Nanotechnology (2018), | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.projectID | TEC2016-77785-P | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/8626313 | es |
dc.identifier.doi | 10.1109/NANO.2018.8626313 | es |
dc.contributor.group | Universidad de Sevilla. TEP-108: Robótica y Tecnología de Computadores Aplicada a la Rehabilitación | es |
idus.format.extent | 5 | es |
dc.eventtitle | IEEE-NANO 2018: 18th International Conference on Nanotechnology | es |
dc.eventinstitution | Cork, Ireland | es |
dc.relation.publicationplace | New York, USA | es |