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dc.creatorGuerra Vinuesa, Oscares
dc.creatorEscalera Morón, Saraes
dc.creatorRosa Utrera, José Manuel de laes
dc.creatorRío Fernández, Rocío deles
dc.creatorMedeiro Hidalgo, Fernandoes
dc.creatorRodríguez Vázquez, Ángel Benito
dc.date.accessioned2020-01-27T14:59:28Z
dc.date.available2020-01-27T14:59:28Z
dc.date.issued2005
dc.identifier.citationGuerra Vinuesa, O., Escalera Morón, S., Rosa Utrera, J.M.d.l., Río Fernández, R.d., Medeiro Hidalgo, F. y Rodríguez Vázquez, Á.B. (2005). A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 ΣΔ modulator with programmable gain and programmable chopper stabilization. En VLSI Circuits and Systems II (71-82), Sevilla, España: The International Society for Optical Engineering - SPIE.
dc.identifier.issn0277-786Xes
dc.identifier.urihttps://hdl.handle.net/11441/92359
dc.description.abstractThis paper describes a 0.35μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade ΣDelta; modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator includes a programmable set of gains (x0.5, x1, x2, and x4) and a programmable set of chopper frequencies (fs/16, fs/8, fs/4 and fs/2). It has also been designed to operate within the restrictive environmental conditions of automotive electronics (-40°C, 175°C). The modulator architecture has been selected after an exhaustive comparison among multiple ΣΔM topologies in terms of resolution, speed and power dissipation. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12MHz and consumes, all together, 14.7mW from a single 3.3-V supply. Experimental measurements result in 99.77dB of Dynamic Range (DR), which combined with the gain programmability leads to an overall DR of 112dB. This puts the presented design beyond the state-of-the-art according with the existing bibliography.es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherThe International Society for Optical Engineering - SPIEes
dc.relation.ispartofVLSI Circuits and Systems II (2005), pp. 71-82.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectσΔ modulatores
dc.subjectChopper stabilizationes
dc.subjectGain programmabilityes
dc.titleA 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 ΣΔ modulator with programmable gain and programmable chopper stabilizationes
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.publisherversionhttp://dx.doi.org/10.1117/12.608304es
dc.identifier.doi10.1117/12.608304es
idus.format.extent12 p.es
dc.publication.initialPage71es
dc.publication.endPage82es
dc.eventtitleVLSI Circuits and Systems IIes
dc.eventinstitutionSevilla, Españaes
dc.identifier.sisius5516043es

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