dc.creator | Tortosa Navas, Ramón | es |
dc.creator | Rosa Utrera, José Manuel de la | es |
dc.creator | Rodríguez Vázquez, Ángel Benito | es |
dc.creator | Fernández Fernández, Francisco Vidal | es |
dc.date.accessioned | 2020-01-24T14:24:37Z | |
dc.date.available | 2020-01-24T14:24:37Z | |
dc.date.issued | 2005 | |
dc.identifier.citation | Tortosa Navas, R., Rosa Utrera, J.M.d.l., Rodríguez Vázquez, Á.B. y Fernández Fernández, F.V. (2005). Continuous-time cascaded ΣΔ modulators for VDSL: A comparative study. En VLSI Circuits and Systems II (59-70), Sevilla, España: The International Society for Optical Engineering - SPIE. | |
dc.identifier.issn | 0277-786X | es |
dc.identifier.uri | https://hdl.handle.net/11441/92293 | |
dc.description.abstract | This paper describes new cascaded continuous-time ΣΔ modulators intended to cope with very high-rate digital subscriber line specifications, i.e 12-bit resolution within a 20-MHz signal bandwidth. These modulators have been synthesized using a new methodology that is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. This method allows to place the zeroes/poles of the loop-filter transfer function in an optimal way and to reduce the number of analog components, namely, transconductors and/or amplifiers, resistors, capacitors and digital-to-analog converters. This leads to more efficient topologies in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealities. A comparison study of the synthesized architectures is done considering their sensitivity to most critical circuit error mechanisms. Time-domain behavioral simulations are shown to validate the presented approach. | es |
dc.description.sponsorship | Ministerio de Educación y Ciencia TEC2004-01752/MIC | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | The International Society for Optical Engineering - SPIE | es |
dc.relation.ispartof | VLSI Circuits and Systems II (2005), p 59-70 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Analog-to-digital converters | es |
dc.subject | Continuous-time circuits | es |
dc.subject | Sigma-delta modulators | es |
dc.title | Continuous-time cascaded ΣΔ modulators for VDSL: A comparative study | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TEC2004-01752/MIC | es |
dc.relation.publisherversion | http://dx.doi.org/10.1117/12.607923 | es |
dc.identifier.doi | 10.1117/12.607923 | es |
idus.format.extent | 12 p. | es |
dc.publication.initialPage | 59 | es |
dc.publication.endPage | 70 | es |
dc.eventtitle | VLSI Circuits and Systems II | es |
dc.eventinstitution | Sevilla, España | es |
dc.identifier.sisius | 5516056 | es |