dc.creator | Iakymchuk, T. | es |
dc.creator | Rosado, A. | es |
dc.creator | Serrano Gotarredona, María Teresa | es |
dc.creator | Linares Barranco, Bernabé | es |
dc.creator | Jiménez Fernández, Ángel Francisco | es |
dc.creator | Linares Barranco, Alejandro | es |
dc.creator | Jiménez Moreno, Gabriel | es |
dc.date.accessioned | 2019-12-26T09:20:28Z | |
dc.date.available | 2019-12-26T09:20:28Z | |
dc.date.issued | 2014 | |
dc.identifier.citation | Iakymchuk, T., Rosado, A., Serrano Gotarredona, T., Linares Barranco, B., Jiménez Fernández, Á.F., Linares Barranco, A. y Jiménez Moreno, G. (2014). An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links. En ISCAS 2014: IEEE International Symposium on Circuits and Systems (1556-1559), Melbourne VIC, Australia: IEEE Computer Society. | |
dc.identifier.isbn | 978-1-4799-3432-4 | es |
dc.identifier.issn | 0271-4302 | es |
dc.identifier.uri | https://hdl.handle.net/11441/91252 | |
dc.description.abstract | Nowadays spike-based brain processing emulation is
taking off. Several EU and others worldwide projects are
demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or
NeuroGrid. The larger the brain process emulation on silicon is,
the higher the communication performance of the hosting
platforms has to be. Many times the bottleneck of these system
implementations is not on the performance inside a chip or a
board, but in the communication between boards. This paper
describes a novel modular Address-Event-Representation (AER)
FPGA-based (Spartan6) infrastructure PCB (the AER-Node
board) with 2.5Gbps LVDS high speed serial links over SATA
cables that offers a peak performance of 32-bit 62.5Meps (Mega
events per second) on board-to-board communications. The
board allows back compatibility with parallel AER devices
supporting up to x2 28-bit parallel data with asynchronous
handshake. These boards also allow modular expansion
functionality through several daughter boards. The paper is
focused on describing in detail the LVDS serial interface and
presenting its performance. | es |
dc.description.sponsorship | Ministerio de Ciencia e Innovación TEC2009-10639-C04-02/01 | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2012-37868-C04-02/01 | es |
dc.description.sponsorship | Junta de Andalucía TIC-6091 | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad PRI-PIMCHI-2011-0768 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | ISCAS 2014: IEEE International Symposium on Circuits and Systems (2014), p 1556-1559 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.projectID | TEC2009-10639-C04-02/01 | es |
dc.relation.projectID | TEC2012-37868-C04-02/01 | es |
dc.relation.projectID | TIC-6091 | es |
dc.relation.projectID | PRI-PIMCHI-2011-0768 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/6865445 | es |
dc.identifier.doi | 10.1109/ISCAS.2014.6865445 | es |
dc.contributor.group | Universidad de Sevilla. TEP-108: Robótica y Tecnología de Computadores Aplicada a la Rehabilitación | es |
idus.format.extent | 4 | es |
dc.publication.initialPage | 1556 | es |
dc.publication.endPage | 1559 | es |
dc.eventtitle | ISCAS 2014: IEEE International Symposium on Circuits and Systems | es |
dc.eventinstitution | Melbourne VIC, Australia | es |
dc.relation.publicationplace | New York, USA | es |