dc.creator | Jiménez Fernández, Ángel Francisco | es |
dc.creator | Linares Barranco, Alejandro | es |
dc.creator | Paz Vicente, Rafael | es |
dc.creator | Jiménez Moreno, Gabriel | es |
dc.creator | Civit Balcells, Antón | es |
dc.date.accessioned | 2019-12-16T12:45:21Z | |
dc.date.available | 2019-12-16T12:45:21Z | |
dc.date.issued | 2010 | |
dc.identifier.citation | Jiménez Fernández, Á.F., Linares Barranco, A., Paz Vicente, R., Jiménez Moreno, G. y Civit Balcells, A. (2010). Building Blocks for Spikes Signals Processing. En IJCNN 2010 : International Joint Conference on Neural Networks Barcelona, España: IEEE Computer Society. | |
dc.identifier.isbn | 978-1-4244-6916-1 | es |
dc.identifier.issn | 2161-4393 | es |
dc.identifier.uri | https://hdl.handle.net/11441/90975 | |
dc.description.abstract | Neuromorphic engineers study models and
implementations of systems that mimic neurons behavior in the
brain. Neuro-inspired systems commonly use spikes to
represent information. This representation has several
advantages: its robustness to noise thanks to repetition, its
continuous and analog information representation using digital
pulses, its capacity of pre-processing during transmission time,
... , Furthermore, spikes is an efficient way, found by nature, to
codify, transmit and process information. In this paper we
propose, design, and analyze neuro-inspired building blocks
that can perform spike-based analog filters used in signal
processing. We present a VHDL implementation for FPGA.
Presented building blocks take advantages of the spike rate
coded representation to perform a massively parallel processing
without complex hardware units, like floating point arithmetic
units, or a large memory. Those low requirements of hardware
allow the integration of a high number of blocks inside a FPGA,
allowing to process fully in parallel several spikes coded signals. | es |
dc.description.sponsorship | Junta de Andalucía P06-TIC-O1417 | es |
dc.description.sponsorship | Ministerio de Ciencia e Innovación TEC2009-10639-C04-02 | es |
dc.description.sponsorship | Ministerio de Ciencia e Innovación TEC2006-11730-C03-02 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | IJCNN 2010 : International Joint Conference on Neural Networks (2010), | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Building Blocks for Spikes Signals Processing | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.projectID | P06-TIC-O1417 | es |
dc.relation.projectID | TEC2009-10639-C04-02 | es |
dc.relation.projectID | TEC2006-11730-C03-02 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/5596845 | es |
dc.identifier.doi | 10.1109/IJCNN.2010.5596845 | es |
idus.format.extent | 8 | es |
dc.eventtitle | IJCNN 2010 : International Joint Conference on Neural Networks | es |
dc.eventinstitution | Barcelona, España | es |
dc.relation.publicationplace | New York, USA | es |