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dc.creatorBerner, Raphaeles
dc.creatorDelbruck, Tobiases
dc.creatorCivit Balcells, Antónes
dc.creatorLinares Barranco, Alejandroes
dc.date.accessioned2019-12-12T09:02:12Z
dc.date.available2019-12-12T09:02:12Z
dc.date.issued2007
dc.identifier.citationBerner, R., Delbruck, T., Civit Balcells, A. y Linares Barranco, A. (2007). A 5 Meps 00 USB2.0 Address-Event Monitor-Sequencer Interface. En ISCAS 2007: IEEE International Symposium on Circuits and Systems (2451-2454), New Orleans, USA: IEEE Computer Society.
dc.identifier.isbn1-4244-0920-9es
dc.identifier.issn0271-4302es
dc.identifier.urihttps://hdl.handle.net/11441/90827
dc.description.abstractThis paper describes a high-speed USB2.0 Address- Event Representation (AER) interface that allows simultaneous monitoring and sequencing of precisely timed AER data. This low-cost (<$100), two chip, bus powered interface can achieve sustained AER event rates of 5 megaevents per second (Meps). Several boards can be electrically synchronized, allowing simultaneous synchronized capture from multiple devices. It has three AER ports, one for sequencing, one for monitoring and one for passing through the monitored events. This paper also describes the host software infrastructure that makes the board usable for a heterogeneous mixture of AER devices and that allows recording and playback of recorded data.es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherIEEE Computer Societyes
dc.relation.ispartofISCAS 2007: IEEE International Symposium on Circuits and Systems (2007), p 2451-2454
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.titleA 5 Meps $100 USB2.0 Address-Event Monitor-Sequencer Interfacees
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadoreses
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/4253172es
dc.identifier.doi10.1109/ISCAS.2007.378616es
idus.format.extent4es
dc.publication.initialPage2451es
dc.publication.endPage2454es
dc.eventtitleISCAS 2007: IEEE International Symposium on Circuits and Systemses
dc.eventinstitutionNew Orleans, USAes
dc.relation.publicationplaceNew York, USAes

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