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dc.creatorGarcía Vargas, Ignacioes
dc.creatorSenhadji Navarro, Raoufes
dc.date.accessioned2019-12-10T09:16:12Z
dc.date.available2019-12-10T09:16:12Z
dc.date.issued2015
dc.identifier.citationGarcía Vargas, I. y Senhadji Navarro, R. (2015). Finite State Machines With Input Multiplexing: A Performance Study. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34 (5), 867-871.
dc.identifier.issn0278-0070es
dc.identifier.urihttps://hdl.handle.net/11441/90785
dc.description.abstractFinite state machines with input multiplexing (FSMIMs) have been proposed in previous works as a technique for efficient mapping FSMs into ROM memory. In this paper, we propose a new architecture for implementing FSMIMs, called FSMIM with state-based input selection, whose goal is to achieve a further reduction in memory usage. This paper also describes in detail the algorithms for generating FSMIMs used by the tool FSMIM-Gen, which has been developed and made available on the Internet for free public use. A comparative study in terms of speed and area between FSMIM approaches and other field programmable gate array-based techniques is presented. The results show that the FSMIM approaches obtain huge reductions in the look-up table (LUT) usage by using a small number of embedded memory blocks. In addition, speed improvements over conventional LUT-based implementations have been obtained in many cases.es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherIEEE Computer Societyes
dc.relation.ispartofIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34 (5), 867-871.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectEmbedded memory blocks (EMBs)es
dc.subjectFinite state machine (FSM)es
dc.subjectField programmable gate array (FPGA)es
dc.subjectLogic synthesises
dc.subjectROMes
dc.titleFinite State Machines With Input Multiplexing: A Performance Studyes
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadoreses
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/7047691es
dc.identifier.doi10.1109/TCAD.2015.2406859es
idus.format.extent5es
dc.journaltitleIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemses
dc.publication.volumen34es
dc.publication.issue5es
dc.publication.initialPage867es
dc.publication.endPage871es

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