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dc.creatorPérez Prieto, Norbertoes
dc.creatorValtierra, José Luises
dc.creatorDelgado Restituto, Manueles
dc.creatorRodríguez Vázquez, Ángel Benitoes
dc.date.accessioned2019-11-29T15:50:26Z
dc.date.available2019-11-29T15:50:26Z
dc.date.issued2019
dc.identifier.citationPérez Prieto, N., Valtierra, J.L., Delgado Restituto, M. y Rodríguez Vázquez, Á.B. (2019). A Sub-μVRms Chopper Front-End for ECoG Recording. En IEEE International Symposium on Circuits and Systems (ISCAS) Sapporo, Japón: Institute of Electrical and Electronics Engineers.
dc.identifier.isbn978-1-7281-0397-6es
dc.identifier.issn2158-1525es
dc.identifier.urihttps://hdl.handle.net/11441/90648
dc.description.abstractThis paper presents a low-noise, low-power fully differential chopper-modulated front-end circuit intended for ECoG signal recording. Among other features, it uses a subthreshold source-follower biquad in the forward path to reduce noise and avoid the implementation of a ripple rejection loop. The prototype was designed in 0.18μm CMOS technology with a 1V supply. Post-layout simulations were carried out showing a power consumption below 2μW and an integrated input-referred noise of 0.75μV rms , with a noise floor below 50 nV√Hz, over a bandwidth from 1 to 200Hz, for a noise efficiency factor of 2.7.es
dc.description.sponsorshipMinisterio de Economía y Empresa TEC2016-80923-Pes
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineerses
dc.relation.ispartofIEEE International Symposium on Circuits and Systems (ISCAS) (2019),
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectBrain Machine Interfaceses
dc.subjectAnalog front-endes
dc.subjectNeural Recordinges
dc.subjectChopperes
dc.subjectLow Noisees
dc.subjectLow Poweres
dc.subjectFront-Endes
dc.subjectLNAes
dc.subjectECoGes
dc.titleA Sub-μVRms Chopper Front-End for ECoG Recordinges
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDTEC2016-80923-Pes
dc.relation.publisherversionhttps://doi.org/10.1109/ISCAS.2019.8702599es
dc.identifier.doi10.1109/ISCAS.2019.8702599es
idus.format.extent5 p.es
dc.eventtitleIEEE International Symposium on Circuits and Systems (ISCAS)es
dc.eventinstitutionSapporo, Japónes

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