dc.creator | Vidal Verdú, Fernando | es |
dc.creator | Navas González, Rafael | es |
dc.creator | Rodríguez Vázquez, Ángel Benito | es |
dc.date.accessioned | 2019-10-17T14:43:40Z | |
dc.date.available | 2019-10-17T14:43:40Z | |
dc.date.issued | 1998 | |
dc.identifier.citation | Vidal Verdú, F., Navas González, R. y Rodríguez Vázquez, Á.B. (1998). Mixed signal CMOS high precision circuits for on chip learning. En 1998 IEEE International Symposium on Circuits and Systems (ISCAS) (111-50-111-53), Monterrey, USA: Institute of Electrical and Electronics Engineers. | |
dc.identifier.isbn | 0-7803-4455-3 | es |
dc.identifier.uri | https://hdl.handle.net/11441/89729 | |
dc.description.abstract | Learning algorithms have become of great interest to be applied not only to neural or hybrid neuro-fuzzy systems, but also as a tool to achieve a fine tuning of analog circuits, whose main drawback is their lack of precision. This paper presents accurate, discrete-time CMOS building blocks to implement learning rules on-chip. Specifically, a voltage mode high precision comparator as well as an absolute value circuit. These blocks, plus multiplexing in time techniques, are used to build a circuit to determine the polarity of the learning increments. An exemplary circuit has been simulated with HSPICE with the parameters of a 1 /spl mu/m CMOS technology. Statistical variations of technological parameters were considered. The results show that all curves from 30 runs of a Monte Carlo analysis behave as expected, and at least 8 bits of resolution are achieved by the proposed techniques. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | 1998 IEEE International Symposium on Circuits and Systems (ISCAS) (1998), p 111-50-111-53 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Mixed signal CMOS high precision circuits for on chip learning | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.publisherversion | https://doi.org/10.1109/ISCAS.1998.703894 | es |
dc.identifier.doi | 10.1109/ISCAS.1998.703894 | es |
idus.format.extent | 4 p. | es |
dc.publication.initialPage | 111-50 | es |
dc.publication.endPage | 111-53 | es |
dc.eventtitle | 1998 IEEE International Symposium on Circuits and Systems (ISCAS) | es |
dc.eventinstitution | Monterrey, USA | es |
dc.identifier.sisius | 5598568 | es |