Some design trade-offs for large CNN chips using small-size transistors

Abstract

Small-size MOS transistors (MOST) exhibit a bunch of second-order effects which limit their application to design Cellular Neural Network (CNN) chips. The inverse dependency of mismatch with transistor sizes may result in severe accuracy degradation. Also, because of the down scaling of supply voltages with the technology feature size, noise and distortion produce large additional errors in submicron technologies. To reduce the influence of all these errors requires one to properly choose the interconnection synapse circuitry, to perform intensive parametric optimization, and to use large enough transistor sizes. Consequently, the cell density and the operation speed cannot be scaled up to their limits because they have to be traded-off for accuracy. This trade-off is illustrated by the evaluation of the composed Power/(Precision/spl times/Speed) figure, which gives results independent of the sizes. In addition to the parametric errors, catastrophic faults impose a limit on the maximum chip size for given yield, and open the issues of fast go/no-go testing, fault-driven reconfiguration and/or multi-chip architectures.