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dc.creatorGarcía Vargas, Ignacioes
dc.creatorGalán, Marianoes
dc.creatorFernández Fernández, Francisco Vidales
dc.creatorRodríguez Vázquez, Ángel Benitoes
dc.date.accessioned2019-10-03T17:34:50Z
dc.date.available2019-10-03T17:34:50Z
dc.date.issued1997
dc.identifier.citationGarcía Vargas, I., Galán, M., Fernández Fernández, F.V. y Rodríguez Vázquez, Á.B. (1997). An algorithm for numerical reference generation in symbolic analysis of large analog circuits. En Proceedings European Design and Test Conference (395-399), París, Francia: Institute of Electrical and Electronics Engineers.
dc.identifier.isbn0-8186-7786-4es
dc.identifier.urihttps://hdl.handle.net/11441/89436
dc.description.abstractThis paper addresses the problems arising in the calculation of numerical references (network function coefficients), essential for an appropriate error control in simplification before and during generation algorithms for symbolic analysis of large analog circuits. The conventional polynomial interpolation method reveals to be unable to handle the large circuit sizes needed, mainly due to the dramatic effect of round-off errors. This paper introduces a new algorithm able to accurately calculate the network function coefficients of large analog circuits in an efficient way.es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineerses
dc.relation.ispartofProceedings European Design and Test Conference (1997), p 395-399
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.titleAn algorithm for numerical reference generation in symbolic analysis of large analog circuitses
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.publisherversionhttp://dx.doi.org/10.1109/EDTC.1997.582390es
dc.identifier.doi10.1109/EDTC.1997.582390es
idus.format.extent5 p.es
dc.publication.initialPage395es
dc.publication.endPage399es
dc.eventtitleProceedings European Design and Test Conferencees
dc.eventinstitutionParís, Franciaes

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