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An Embedded 12-bit 80MS/s A/D/A Interface for Power-Line Communications in 0.13μm Pure Digital CMOS Technology

dc.creatorDelgado Restituto, Manueles
dc.creatorRuiz Amaya, Jesúses
dc.creatorRosa Utrera, José Manuel de laes
dc.creatorFernández Bootello, Juan Franciscoes
dc.creatorDíez Villar, Leilaes
dc.creatorRío Fernández, Rocío deles
dc.creatorRodríguez Vázquez, Ángel Benitoes
dc.date.accessioned2019-09-17T13:52:22Z
dc.date.available2019-09-17T13:52:22Z
dc.date.issued2005
dc.identifier.citationDelgado Restituto, M., Ruiz Amaya, J., Rosa Utrera, J.M.d.l., Fernández Bootello, J.F., Díez Villar, L., Río Fernández, R.d. y Rodríguez Vázquez, Á.B. (2005). An Embedded 12-bit 80MS/s A/D/A Interface for Power-Line Communications in 0.13μm Pure Digital CMOS Technology. En Proceeding of the 2005 International Symposium on Circuits and Systems (ISCAS) (4626-4629), Kobe, Japón: Institute of Electrical and Electronics Engineers.
dc.identifier.urihttps://hdl.handle.net/11441/89182
dc.description.abstractThis paper presents an embedded interface, comprising both A/D and D/A converters, which has been implemented in a 0.13μm pure digital CMOS technology. The interface is integrated in a system for high-performance broad-band power-line communications. The A/D converter uses a pipelined structure, whereas the D/A stage is based on segmented current steering techniques. In both cases, specifications are 12-b resolution at 80MS/s and MTPR above 56dB.es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineerses
dc.relation.ispartofProceeding of the 2005 International Symposium on Circuits and Systems (ISCAS) (2005), p 4626-4629
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectPipeline Analog-to-Digital Converteres
dc.subjectCurrent Steering Digital-to-Analog Converteres
dc.subjectData Converterses
dc.subjectEmbedded Converterses
dc.titleAn Embedded 12-bit 80MS/s A/D/A Interface for Power-Line Communications in 0.13μm Pure Digital CMOS Technologyes
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
idus.format.extent4 p.es
dc.publication.initialPage4626es
dc.publication.endPage4629es
dc.eventtitleProceeding of the 2005 International Symposium on Circuits and Systems (ISCAS)es
dc.eventinstitutionKobe, Japónes

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