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Pixel design and evaluation in CMOS image sensor technology

dc.creatorVargas Sierra, Soniaes
dc.creatorRoca Moreno, Elisendaes
dc.creatorLiñán Cembrano, Gustavoes
dc.date.accessioned2018-12-03T10:28:58Z
dc.date.available2018-12-03T10:28:58Z
dc.date.issued2009
dc.identifier.citationVargas Sierra, S., Roca Moreno, E. y Liñán Cembrano, G. (2009). Pixel design and evaluation in CMOS image sensor technology. En XXIV Conference on Design of Circuits and Integrated Systems, Zaragoza (España).
dc.identifier.urihttps://hdl.handle.net/11441/80735
dc.description.abstractA chip designed in a 0.18 μm CMOS Image Sensor Technology (CIS) is presented which incorporates different pixel design alternatives for Active Pixel Sensor (APS). CIS technology improves characteristics such as sensitivity, dark current and noise, that are strongly layout dependent. This chip includes a set of pixel architectures where different parameters have been modified: layout of active diffusion, threshold voltage of the source follower transistor and the use of microlenses. Besides, structures to study the influence of crosstalk between pixels have been incorporated.es
dc.formatapplication/pdfes
dc.language.isoenges
dc.relation.ispartofXXIV Conference on Design of Circuits and Integrated Systems (2009), p 1-6
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectImage Sensorses
dc.subjectActive Pixels Sensores
dc.subjectCIS Technologyes
dc.titlePixel design and evaluation in CMOS image sensor technologyes
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
idus.format.extent6 p.es
dc.publication.initialPage1es
dc.publication.endPage6es
dc.eventtitleXXIV Conference on Design of Circuits and Integrated Systemses
dc.eventinstitutionZaragoza (España)es

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