dc.creator | Leñero Bardallo, Juan Antonio | es |
dc.creator | Serrano Gotarredona, María Teresa | es |
dc.creator | Linares Barranco, Bernabé | es |
dc.date.accessioned | 2018-07-23T08:30:06Z | |
dc.date.available | 2018-07-23T08:30:06Z | |
dc.date.issued | 2008 | |
dc.identifier.citation | Leñero Bardallo, J.A., Serrano Gotarredona, M.T. y Linares Barranco, B. (2008). A calibration technique for very low current and compact tunable neuromorphic cells: Application to 5-bit 20nA DACs. IEEE Transactions on Circuits and Systems II: Express Briefs, 55 (6), 522-526. | |
dc.identifier.issn | 1549-7747 | es |
dc.identifier.uri | https://hdl.handle.net/11441/77502 | |
dc.description.abstract | Low current applications, like neuromorphic circuits, where operating currents can be as low as a few nanoamperes or less, suffer from huge transistor mismatches, resulting in around or less than 1-bit precisions. Recently, a neuromorphic programmable- kernel 2-D convolution chip has been reported where each pixel included two compact calibrated digital-to-analog converters (DACs) of 5-bit resolution, for currents down to picoamperes. Those DACs were based on MOS ladder structures, which although compact require unit transistors ( is the number of calibration bits). Here, we present a new calibration approach not based on ladders, but on individually calibratable current sources made with MOS transistors of digitally adjustable length, which require only -sized transistors. The scheme includes a translinear circuit-based tuning scheme, which allows us to expand the operating range of the calibrated circuits with graceful precision degradation, over four decades of operating currents. Experimental results are provided for 5-bit resolution DACs operating at 20 nA using two different translinear tuning schemes. Maximum measured precision is 5.05 and 7.15 b, respectively, for the two DAC schemes. | es |
dc.description.sponsorship | Gobierno de España TEC2006-11730-C03-01, TEC-417 | es |
dc.description.sponsorship | European Union IST-2001-34124 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Transactions on Circuits and Systems II: Express Briefs, 55 (6), 522-526. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Analog | es |
dc.subject | Calibration | es |
dc.subject | Mismatch | es |
dc.subject | Subthreshold | es |
dc.title | A calibration technique for very low current and compact tunable neuromorphic cells: Application to 5-bit 20nA DACs | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TEC2006-11730-C03-01 | es |
dc.relation.projectID | TEC-417 | es |
dc.relation.projectID | IST-2001-34124 | es |
dc.relation.publisherversion | http://dx.doi.org/10.1109/TCSII.2007.916864 | es |
dc.identifier.doi | 10.1109/TCSII.2007.916864 | es |
idus.format.extent | 5 p. | es |
dc.journaltitle | IEEE Transactions on Circuits and Systems II: Express Briefs | es |
dc.publication.volumen | 55 | es |
dc.publication.issue | 6 | es |
dc.publication.initialPage | 522 | es |
dc.publication.endPage | 526 | es |
dc.contributor.funder | Gobierno de España | |
dc.contributor.funder | European Union (UE) | |