dc.creator | Domínguez Morales, Manuel Jesús | es |
dc.creator | Linares Barranco, Alejandro | es |
dc.creator | Íñigo Blasco, Pablo | es |
dc.creator | Font Calvo, Juan Luis | es |
dc.creator | Cascado Caballero, Daniel | es |
dc.creator | Jiménez Moreno, Gabriel | es |
dc.creator | Díaz del Río, Fernando | es |
dc.creator | Sevillano Ramos, José Luis | es |
dc.date.accessioned | 2018-05-24T09:52:12Z | |
dc.date.available | 2018-05-24T09:52:12Z | |
dc.date.issued | 2012 | |
dc.identifier.citation | Domínguez Morales, M.J., Linares Barranco, A., Íñigo Blasco, P., Font Calvo, J.L., Cascado Caballero, D., Jiménez Moreno, G.,...,Sevillano Ramos, J.L. (2012). A PCI AER Co-Processor Evaluation Based on CPUs Performance Counters. Journal of Internet Technology, 13 (4), 533-541. | |
dc.identifier.issn | 1607-9264 | es |
dc.identifier.uri | https://hdl.handle.net/11441/75066 | |
dc.description.abstract | Image processing in digital computer systems usually considers the visual information as a sequence of frames. These frames are from cameras that capture reality for a short period of time. They are renewed and transmitted at a rate of 25-30 frames per second, in a typical real-time scenario. Digital video processing has to process each frame in order to obtain a filter result or detect a feature on the input. This processing is usually based on very complex and expensive (in resources) operations for an efficient real-time application. Brain can perform very complex visual processing in real-time using relatively simple cells, called neurons, which codify the information into spikes. Spike-based processing is a relatively new approach that implements the processing by manipulating spikes one by one at the time they are transmitted, like a human brain. The spike-based philosophy for visual information processing based on the neuro-inspired Address Event Representation (AER) is achieving nowadays very high performances. In this work we study the low level performance for real-time scenarios of a spike-based co-processor connected to a conventional PC and implemented through a PCI board. These low level lacks are focused both in the software conversion of static frames into AER format and in the bottleneck of the PCI interface. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | JIT Editorial Office, Library and Information Center, National Dong Hwa University | es |
dc.relation.ispartof | Journal of Internet Technology, 13 (4), 533-541. | |
dc.rights | Atribución-NoComercial-SinDerivadas 3.0 Estados Unidos de América | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Spiking neurons | es |
dc.subject | Address-Event | es |
dc.subject | PCI | es |
dc.subject | FPGA | es |
dc.subject | Synthetic AER generation | es |
dc.title | A PCI AER Co-Processor Evaluation Based on CPUs Performance Counters | es |
dc.type | info:eu-repo/semantics/article | es |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.publisherversion | http://jit.ndhu.edu.tw/ojs/index.php/jit/article/view/801 | es |
dc.contributor.group | Universidad de Sevilla. TEP-108: Robótica y Tecnología de Computadores Aplicada a la Rehabilitación | es |
idus.format.extent | 8 p. | es |
dc.journaltitle | Journal of Internet Technology | es |
dc.publication.volumen | 13 | es |
dc.publication.issue | 4 | es |
dc.publication.initialPage | 533 | es |
dc.publication.endPage | 541 | es |
dc.identifier.sisius | 20354896 | es |