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dc.creatorQuintero Álvarez, Héctor Javieres
dc.creatorAvedillo de Juan, María Josées
dc.creatorNúñez Martínez, Juanes
dc.date.accessioned2018-05-04T13:34:16Z
dc.date.available2018-05-04T13:34:16Z
dc.date.issued2016
dc.identifier.citationQuintero Álvarez, H.J., Avedillo de Juan, M.J. y Nuñez Martínez, J. (2016). Improving robustness of dynamic logic based pipelines. En Design of Circuits and Integrated Systems (DCIS) (1-5), Institute of Electrical and Electronics Engineers.
dc.identifier.urihttps://hdl.handle.net/11441/74102
dc.description.abstractDomino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in addition to the functional limitation associated to the noninverting behavior of Domino gates, there are also robustness disadvantages when compared to inverting dynamic gates. We analyze and compare the tolerance to parameter and operating conditions variations of gate-level pipelines implemented with Domino and with DOE, an inverting dynamic gate we have recently proposed. Our experiments confirm that DOE pipelines are more robust and that improvements are due to its noninverting feature.es
dc.description.sponsorshipMinisterio de Economía y Competitividad FEDER TEC2013-40670-Pes
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineerses
dc.relation.ispartofDesign of Circuits and Integrated Systems (DCIS) (2016), pp. 1-5.
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 Estados Unidos de América*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectNanopipelinees
dc.subjectDynamic logices
dc.subjectRobust design techniqueses
dc.titleImproving robustness of dynamic logic based pipelineses
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDTEC2013-40670-Pes
dc.relation.publisherversionhttps://doi.org/10.1109/DCIS.2015.7388597es
dc.identifier.doi10.1109/DCIS.2015.7388597es
idus.format.extent5 p.es
dc.publication.initialPage1es
dc.publication.endPage5es
dc.eventtitleDesign of Circuits and Integrated Systems (DCIS)es
dc.contributor.funderMinisterio de Economía y Competitividad (MINECO). España

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