dc.creator | Quintero Álvarez, Héctor Javier | es |
dc.creator | Avedillo de Juan, María José | es |
dc.creator | Núñez Martínez, Juan | es |
dc.date.accessioned | 2018-05-04T13:34:16Z | |
dc.date.available | 2018-05-04T13:34:16Z | |
dc.date.issued | 2016 | |
dc.identifier.citation | Quintero Álvarez, H.J., Avedillo de Juan, M.J. y Nuñez Martínez, J. (2016). Improving robustness of dynamic logic based pipelines. En Design of Circuits and Integrated Systems (DCIS) (1-5), Institute of Electrical and Electronics Engineers. | |
dc.identifier.uri | https://hdl.handle.net/11441/74102 | |
dc.description.abstract | Domino dynamic circuits are widely used in
critical parts of high performance systems. In this paper we show
that, in addition to the functional limitation associated to the noninverting
behavior of Domino gates, there are also robustness
disadvantages when compared to inverting dynamic gates. We
analyze and compare the tolerance to parameter and operating
conditions variations of gate-level pipelines implemented with
Domino and with DOE, an inverting dynamic gate we have
recently proposed. Our experiments confirm that DOE pipelines
are more robust and that improvements are due to its noninverting
feature. | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad FEDER TEC2013-40670-P | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | Design of Circuits and Integrated Systems (DCIS) (2016), pp. 1-5. | |
dc.rights | Atribución-NoComercial-SinDerivadas 3.0 Estados Unidos de América | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Nanopipeline | es |
dc.subject | Dynamic logic | es |
dc.subject | Robust design techniques | es |
dc.title | Improving robustness of dynamic logic based pipelines | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TEC2013-40670-P | es |
dc.relation.publisherversion | https://doi.org/10.1109/DCIS.2015.7388597 | es |
dc.identifier.doi | 10.1109/DCIS.2015.7388597 | es |
idus.format.extent | 5 p. | es |
dc.publication.initialPage | 1 | es |
dc.publication.endPage | 5 | es |
dc.eventtitle | Design of Circuits and Integrated Systems (DCIS) | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | |