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dc.creatorNúñez Martínez, Juanes
dc.creatorAvedillo de Juan, María Josées
dc.date.accessioned2018-04-12T16:36:32Z
dc.date.available2018-04-12T16:36:32Z
dc.date.issued2016
dc.identifier.citationNuñez Martínez, J. y Avedillo de Juan, M.J. (2016). Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas. IEEE Journal on Electron Devices, 63 (12), 5012-5020.
dc.identifier.issn0018-9383es
dc.identifier.urihttps://hdl.handle.net/11441/72621
dc.description.abstractIn this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas.es
dc.description.sponsorshipMinisterio de Economía y Competitividad TEC2013-40670-Pes
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineerses
dc.relation.ispartofIEEE Journal on Electron Devices, 63 (12), 5012-5020.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectTunnel transistorses
dc.subjectSteep subthreshold slopees
dc.subjectLow poweres
dc.subjectEnergy efficienyes
dc.subjectLow supply voltagees
dc.titleComparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areases
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDTEC2013-40670-Pes
dc.relation.publisherversionhttps://doi.org/10.1109/TED.2016.2616891es
dc.identifier.doi10.1109/TED.2016.2616891es
idus.format.extent8 p.es
dc.journaltitleIEEE Journal on Electron Deviceses
dc.publication.volumen63es
dc.publication.issue12es
dc.publication.initialPage5012es
dc.publication.endPage5020es
dc.contributor.funderMinisterio de Economía y Competitividad (MINECO). España

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