Diseño sistemático de circuitos analógicos y de señal mixta reconfigurables

Abstract

During the last decades, there has been an increasing demand of electronic devices, mostly in the field of mobile communications. Every year, hand-held communication devices must include more and more functionalities and support an increasing number of different communication standards in order to satisfy the necessities of nowadays society. In order to be able to answer the market demands, those devices should not increase the area occupation while the power consumption is at reasonable levels and, more importantly, the time-to-market factor must be reduced as much as possible. In this scenario, reconfigurable analog and mixed-signal circuits are ideal for such requirements, since they are able to reuse the same blocks to work in different operation modes, which increases the hardware-sharing and reduces the total area occupation of the devices. Besides, they can adapt their power consumption dynamically depending on the application demands, increasing the battery life of such devices. However, reconfigurable circuits are even more complex to design than regular ones. Moreover, the available CAD-tools for analog design are far from the level of automatization that is found in the digital domain. Therefore, the use of systematic design methodologies is mandatory to avoid increasing the design time critically. During the last years, bottom-up methodologies have appeared as promising alternatives of more traditional top-down approaches. These methodologies rely on the use of the Pareto-optimal fronts (PoFs) of the basic building blocks of a complex system, which are a representation of the best achievable trade-offs between the circuit performances. The PoF of the complete system is obtained by composing hierarchically the PoFs of the basic building blocks, from the bottom up to the top-level. This methodology is so advantageous because every design of the PoF at the top-level points to a fully sized design of each one of the lower level blocks, which help reducing the design time of the system. Besides, the PoFs of basic building blocks can be reused, avoiding the tedious and time-consuming generation of PoFs of low-level blocks every time a different system is considered. However, there is no reference in the literature illustrating bottom-up methodologies applied to reconfigurable circuits. Adding support for the use of reconfigurable building blocks in these methodologies would mean a huge advance in the field of systematic design methodologies of analog and mixed-signal circuits. Furthermore, the hierarchical composition of PoFs, either for regular or for reconfigurable circuits, presents implementation issues that have not been addressed and that affect directly to the reusability of PoFs. This thesis aims to contribute to this field by proposing a new design methodology that adds full support to the use of reconfigurable circuits and that solves two important issues related to the hierarchical composition of PoFs and that has not been addressed before. For this, a method to generate PoFs of reconfigurable circuits, which we have called Multi-mode PoFs (mm-PoFs), has been developed. The method is based on the use of a new multi-objective evolutionary algorithm, which is able to optimize the multiple operation modes of the reconfigurable circuits simultaneously. One of the implementation issues of the hierarchical composition of PoFs and mm-Pofs has been solved by introducing a new technique that is able to re-evaluate circuits under different loading conditions without electrical simulation, which improves the reusability of PoFs in the design of different systems. The second issue has been addressed by proposing a new method to efficiently explore efficiently the PoFs of low-level blocks. The presented design methodology is succesfully applied in the design of two different systems. The first application example is the design of a 0.35-um reconfigurable, continuous-time low-pass active filter that must fulfil specification for GSM and DECT standards. The active filter is implemented using a two-stage topology with reconfigurable folded-cascode, Miller-compensated operational amplifiers. For the generation of the mm-PoF of the filter, mm-PoFs of the reconfigurable amplifiers are hierarchicaly composed. In the second application example, the presented methodology is applied in the design of a 130-nm reconfigurable Sigma-Delta modulator that must fulfil specifications for three different standards: GSM, Bluetooth and UMTS. The integrators of the modulator are implemented using reconfigurable folded-cascode operational amplifiers that are able to operate in four different modes by switching the bias current. For the generation of the mm-PoF of the modulator, mm-PoFs of these reconfigurable amplifiers are hierarchically composed.