Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Guerrero Martos, David

doi:10.1007/3-540-45716-X_40

Capítulo de Libro

dc.creator	Ruiz de Clavijo Vázquez, Paulino	es
dc.creator	Juan Chico, Jorge	es
dc.creator	Bellido Díaz, Manuel Jesús	es
dc.creator	Millán Calderón, Alejandro	es
dc.creator	Guerrero Martos, David	es
dc.date.accessioned	2017-01-19T11:58:10Z
dc.date.available	2017-01-19T11:58:10Z
dc.date.issued	2002
dc.identifier.citation	Ruiz de Clavijo Vázquez, P., Juan Chico, J.,...,Guerrero Martos, D. (2002). Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. En Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451 (pp. 400-408). Berlin: Springer.
dc.identifier.isbn	978-3-540-44143-4	es
dc.identifier.issn	0302-9743	es
dc.identifier.uri	http://hdl.handle.net/11441/52479
dc.description.abstract	This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic simulator under development called HALOTIS. The implementation is aimed at efficiency and overall estimations, making it suitable to switching noise evaluation and current peaks localisation. Simulation results and comparison to HSPICE confirm the usefulness and efficiency of the approach.	es
dc.description.sponsorship	Ministerio de Ciencia y Tecnología MODEL project TIC 2000-1350
dc.description.sponsorship	Ministerio de Ciencia y Tecnología VERDI project TIC 2002-2283
dc.format	application/pdf	es
dc.language.iso	eng	es
dc.publisher	Springer	es
dc.relation.ispartof	Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451	es
dc.rights	Attribution-NonCommercial-NoDerivatives 4.0 Internacional	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/4.0/	*
dc.title	Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level	es
dc.type	info:eu-repo/semantics/bookPart	es
dcterms.identifier	https://ror.org/03yxnpp24
dc.type.version	info:eu-repo/semantics/acceptedVersion	es
dc.rights.accessRights	info:eu-repo/semantics/openAccess	es
dc.contributor.affiliation	Universidad de Sevilla. Departamento de Tecnología Electrónica	es
dc.relation.projectID	TIC 2000-1350	es
dc.relation.projectID	TIC 2002-2283	es
dc.relation.publisherversion	http://link.springer.com/chapter/10.1007%2F3-540-45716-X_40	es
dc.identifier.doi	10.1007/3-540-45716-X_40	es
idus.format.extent	9	es
dc.publication.initialPage	400	es
dc.publication.endPage	408	es
dc.relation.publicationplace	Berlin	es
dc.contributor.funder	Ministerio de Ciencia y Tecnología (MCYT). España

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