Ponencia
A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem
Autor/es | Camacho Ruiz, Eros
Sánchez Solano, Santiago Martínez Rodríguez, Macarena Cristina Tena Sánchez, Erica Brox Jiménez, Piedad |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2023-12 |
Fecha de depósito | 2024-01-18 |
Publicado en |
|
ISBN/ISSN | 979-8-3503-0385-8 979-8-3503-0386-5 2640-5563 |
Resumen | As quantum computing technology advances, the security of traditional cryptographic systems is becoming increasingly vulnerable. To address this issue, Post-Quantum Cryptography (PQC) has emerged as a promising solution ... As quantum computing technology advances, the security of traditional cryptographic systems is becoming increasingly vulnerable. To address this issue, Post-Quantum Cryptography (PQC) has emerged as a promising solution that can withstand the brute force of quantum computers. However, PQC is not immune to attacks that exploit weaknesses in implementation, such as Side Channel Attacks (SCAs). SCAs can extract secret keys by analyzing the physical characteristics such as power consumption of the device while performing cryptographic operation. Simple Power Analysis (SPA) is a type of SCA that uses power consumption measurements to extract sensitive information. By applying SPA to a specific hardware implementation of a PQC algorithm such as the NTRU, potential vulnerabilities can appear in the Arithmetic Unit (AU) in charge of the multiplication operation. The effectiveness of this analysis to extract sensitive information has been evaluated through extensive experiments in which different countermeasures and strategies have been proposed, as well as an accelerated algorithm has been implemented. The results demonstrate that SPA can point out security breaches in the NTRU implementation, indicating an issue that can affect the PQC in the future. |
Agencias financiadoras | EU H2020 Grant Agreement No. 952622 EU Horizon Europe research and innovation programme Grant Agreement No. 101119746 MCIN/AEI/10.13039/501100011033 and the EU NextGeneration EU/PRTR Project PID2020-116664RB-100 JUNTA/FEDER SCAROT project 1380823-US |
Identificador del proyecto | EU H2020 952622
EU Horizon Europe 101119746 PID2020-116664RB-100 SCAROT 1380823-US |
Cita | Camacho Ruiz, E., Sánchez Solano, S., Martínez Rodríguez, M.C., Tena Sánchez, E. y Brox Jiménez, P. (2023). A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem. En 2023. 38th Conference on Design of Circuits and Integrated Systems (DCIS) Málaga, Spain: Institute of Electrical and Electronics Engineers. |
Ficheros | Tamaño | Formato | Ver | Descripción |
---|---|---|---|---|
tena-sanchez_malaga_2023_a-sim ... | 2.202Mb | [PDF] | Ver/ | |