Ponencia
Neuron fault tolerance in spiking neural networks
Autor/es | Spyrou, Theofilos
El-Sayed, Sarah A. Afacan, Engin Camuñas Mesa, Luis Alejandro Linares Barranco, Bernabé Stratigopoulos, Haralampos G. |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2021 |
Fecha de depósito | 2023-01-19 |
Publicado en |
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ISBN/ISSN | 1530-1591 |
Resumen | The error-resiliency of Artificial Intelligence (AI)
hardware accelerators is a major concern, especially when they
are deployed in mission-critical and safety-critical applications.
In this paper, we propose a neuron ... The error-resiliency of Artificial Intelligence (AI) hardware accelerators is a major concern, especially when they are deployed in mission-critical and safety-critical applications. In this paper, we propose a neuron fault tolerance strategy for Spiking Neural Networks (SNNs). It is optimized for low area and power overhead by leveraging observations made from a largescale fault injection experiment that pinpoints the critical fault types and locations. We describe the fault modeling approach, the fault injection framework, the results of the fault injection experiment, the fault-tolerance strategy, and the fault-tolerant SNN architecture. The idea is demonstrated on two SNNs that we designed for two SNN-oriented datasets, namely the N-MNIST and IBM’s DVS128 gesture datasets. |
Agencias financiadoras | Junta de Andalucía Universidad de Sevilla |
Identificador del proyecto | US-1260118
VI PPIT USE |
Cita | Spyrou, T., El-Sayed, S.A., Afacan, E., Camuñas Mesa, L.A., Linares Barranco, B. y Stratigopoulos, H.G. (2021). Neuron fault tolerance in spiking neural networks. En 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) (743-748), Grenoble, France: Institute of Electrical and Electronics Engineers. IEEE. |
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