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dc.creatorAvedillo de Juan, María Josées
dc.creatorJiménez, Manueles
dc.creatorNúñez Martínez, Juanes
dc.date.accessioned2022-07-07T11:30:39Z
dc.date.available2022-07-07T11:30:39Z
dc.date.issued2018
dc.identifier.citationAvedillo de Juan, M.J., Jiménez, M. y Núñez Martínez, J. (2018). Phase Transition FETs for Improved Dynamic Logic Gates. IEEE Electron Device Letters, 39 (11), 8471107.
dc.identifier.issnPrint: 0741-3106es
dc.identifier.issnElectronic: 1558-0563es
dc.identifier.urihttps://hdl.handle.net/11441/135121
dc.description.abstractTransistors incorporating phase change materials (Phase Change FETs) are being investigated to obtain steep switching and a boost in the I ON /I OFF ratio and, thus, to solve power and energy limitations of CMOS technologies. In addition to the replacement of the transistors in conventional static CMOS logic circuits, the distinguishing features of Phase Change FETs can be exploited in other application domains or can be useful for solving specific design challenges. In this letter, we take advantage of them to implement a smart dynamic gate in which undesirable contention currents are reduced, leading to speed advantage without power penalties.es
dc.description.sponsorshipMinisterio de Economía y Competitividad FEDER TEC2017-87052-Pes
dc.formatapplication/pdfes
dc.format.extent4 p.es
dc.language.isoenges
dc.publisherIEEEes
dc.relation.ispartofIEEE Electron Device Letters, 39 (11), 8471107.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectSteep subthreshold slopees
dc.subjectPhase transition materialses
dc.subjectLow voltagees
dc.subjectDynamic logices
dc.subjectKeeper transistores
dc.titlePhase Transition FETs for Improved Dynamic Logic Gateses
dc.typeinfo:eu-repo/semantics/articlees
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDTEC2017-87052-Pes
dc.relation.publisherversionhttps://dx.doi.org/10.1109/LED.2018.2871855es
dc.identifier.doi10.1109/LED.2018.2871855es
dc.journaltitleIEEE Electron Device Letterses
dc.publication.volumen39es
dc.publication.issue11es
dc.publication.initialPage8471107es
dc.contributor.funderMinisterio de Economía y Competitividad (MINECO). Españaes
dc.contributor.funderEuropean Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER)es

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