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dc.creatorCano Quiveu, Germánes
dc.creatorRuiz de Clavijo Vázquez, Paulinoes
dc.creatorBellido Díaz, Manuel Jesúses
dc.creatorGuerrero Martos, Davides
dc.creatorViejo Cortés, Juliánes
dc.creatorJuan Chico, Jorgees
dc.date.accessioned2022-02-02T09:52:24Z
dc.date.available2022-02-02T09:52:24Z
dc.date.issued2021
dc.identifier.citationCano Quiveu, G., Ruiz de Clavijo Vázquez, P., Bellido Díaz, M.J., Guerrero Martos, D., Viejo Cortés, J. y Juan Chico, J. (2021). An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation. IEEE Access, 9, 161383-161394.
dc.identifier.issn2169-3536es
dc.identifier.urihttps://hdl.handle.net/11441/129554
dc.description.abstractThis paper introduces a design and on-chip verification framework for IPCores in FPGA platforms. The methodology of the proposed framework is based on the development of a high level software model, an HDL description of the IPCore and the verification of the system under test by the Autotest Core, an on-chip verification core developed for this framework. The test pattern generation is done at the high level in software and used throughout the design and verification process. HDL simulation results can then be compared to on-chip results and get performance measurements from the Autotest Core. The Off-line testing is possible by using standard low-cost Flash storage (SD card). The proposed framework and methodology applied to PRESENT and SPONGENT cryptographic algorithms has shown over two orders of magnitude better performance than commercial tools like Xilinx's VIO and a hardware footprint of the verification cored below 3% of the available FPGA resources.es
dc.description.sponsorshipMinisterio de Economía y Competitividad TIN2017-89951-Pes
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherIEEE Computer Societyes
dc.relation.ispartofIEEE Access, 9, 161383-161394.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectField Programmable Gate Array (FPGA)es
dc.subjectFrameworkes
dc.subjectHDLes
dc.subjectIoTes
dc.subjectIPCorees
dc.subjectOn-chipes
dc.subjectPerformancees
dc.subjectVerificationes
dc.titleAn Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluationes
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/publishedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Tecnología Electrónicaes
dc.relation.projectIDTIN2017-89951-Pes
dc.relation.publisherversionhttps://ieeexplore.ieee.org/abstract/document/9632568es
dc.identifier.doi10.1109/ACCESS.2021.3132188es
dc.journaltitleIEEE Accesses
dc.publication.volumen9es
dc.publication.initialPage161383es
dc.publication.endPage161394es
dc.contributor.funderMinisterio de Economía y Competitividad (MINECO). Españaes

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