dc.creator | Cano Quiveu, Germán | es |
dc.creator | Ruiz de Clavijo Vázquez, Paulino | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Guerrero Martos, David | es |
dc.creator | Viejo Cortés, Julián | es |
dc.creator | Juan Chico, Jorge | es |
dc.date.accessioned | 2022-02-02T09:52:24Z | |
dc.date.available | 2022-02-02T09:52:24Z | |
dc.date.issued | 2021 | |
dc.identifier.citation | Cano Quiveu, G., Ruiz de Clavijo Vázquez, P., Bellido Díaz, M.J., Guerrero Martos, D., Viejo Cortés, J. y Juan Chico, J. (2021). An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation. IEEE Access, 9, 161383-161394. | |
dc.identifier.issn | 2169-3536 | es |
dc.identifier.uri | https://hdl.handle.net/11441/129554 | |
dc.description.abstract | This paper introduces a design and on-chip verification framework for IPCores in FPGA
platforms. The methodology of the proposed framework is based on the development of a high level software
model, an HDL description of the IPCore and the verification of the system under test by the Autotest Core,
an on-chip verification core developed for this framework. The test pattern generation is done at the high
level in software and used throughout the design and verification process. HDL simulation results can then be
compared to on-chip results and get performance measurements from the Autotest Core. The Off-line testing
is possible by using standard low-cost Flash storage (SD card). The proposed framework and methodology
applied to PRESENT and SPONGENT cryptographic algorithms has shown over two orders of magnitude
better performance than commercial tools like Xilinx's VIO and a hardware footprint of the verification
cored below 3% of the available FPGA resources. | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TIN2017-89951-P | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | IEEE Access, 9, 161383-161394. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Field Programmable Gate Array (FPGA) | es |
dc.subject | Framework | es |
dc.subject | HDL | es |
dc.subject | IoT | es |
dc.subject | IPCore | es |
dc.subject | On-chip | es |
dc.subject | Performance | es |
dc.subject | Verification | es |
dc.title | An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | TIN2017-89951-P | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/abstract/document/9632568 | es |
dc.identifier.doi | 10.1109/ACCESS.2021.3132188 | es |
dc.journaltitle | IEEE Access | es |
dc.publication.volumen | 9 | es |
dc.publication.initialPage | 161383 | es |
dc.publication.endPage | 161394 | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | es |