dc.creator | Mohan, Charanraj | es |
dc.creator | Camuñas Mesa, Luis Alejandro | es |
dc.creator | Vianello, Elisa | es |
dc.creator | Reita, Carlo | es |
dc.creator | Rosa Utrera, José Manuel de la | es |
dc.creator | Serrano Gotarredona, María Teresa | es |
dc.creator | Linares Barranco, Bernabé | es |
dc.date.accessioned | 2021-06-28T12:44:16Z | |
dc.date.available | 2021-06-28T12:44:16Z | |
dc.date.issued | 2020 | |
dc.identifier.citation | Mohan, C., Camuñas Mesa, L.A., Vianello, E., Reita, C., Rosa Utrera, J.M.d.l., Serrano Gotarredona, M.T. y Linares Barranco, B. (2020). Experimental Body-input Three-stage DC offset Calibration Scheme for Memristive Crossbar. En 2020 IEEE International Symposium on Circuits and Systems (ISCAS) Sevilla (España): IEEE. | |
dc.identifier.isbn | 978-1-7281-3320-1 | es |
dc.identifier.uri | https://hdl.handle.net/11441/114904 | |
dc.description.abstract | Reading several ReRAMs simultaneously in a neuromorphic
circuit increases power consumption and limits scalability.
Applying small inference read pulses is a vain attempt
when offset voltages of the read-out circuit are decisively more.
This paper presents an experimental validation of a three-stage
calibration scheme to calibrate the DC offset voltage across the
rows of the memristive crossbar. The proposed method is based
on biasing the body terminal of one of the differential pair
MOSFETs of the buffer through a series of cascaded resistor
banks arranged in three stages- coarse, fine and finer stages.
The circuit is designed in a 130 nm CMOS technology, where
the OxRAM-based binary memristors are built on top of it. A
dedicated PCB and other auxiliary boards have been designed
for testing the chip. Experimental results validate the presented
approach, which is only limited by mismatch and electrical noise. | es |
dc.description.sponsorship | EU H2020 grant 687299 NeuRAM3 | es |
dc.description.sponsorship | EU H2020 grant 824164 HERMES | es |
dc.description.sponsorship | EU H2020 grant 871501 NeurONN | es |
dc.description.sponsorship | EU H2020 grant 871371 MeM-Scales | es |
dc.description.sponsorship | Spanish Ministry of Economy and Competitiveness TEC2015-63884-C2-1-P (COGNET) | es |
dc.description.sponsorship | Spanish Ministry of Economy and Competitiveness G0086 ICON | es |
dc.description.sponsorship | Universidad de Sevilla (España) VI PPIT | es |
dc.format | application/pdf | es |
dc.format.extent | 5 p. | es |
dc.language.iso | eng | es |
dc.publisher | IEEE | es |
dc.relation.ispartof | 2020 IEEE International Symposium on Circuits and Systems (ISCAS) (2020). | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Experimental Body-input Three-stage DC offset Calibration Scheme for Memristive Crossbar | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.projectID | 687299 NeuRAM3 | es |
dc.relation.projectID | 824164 HERMES | es |
dc.relation.projectID | 871501 NeurONN | es |
dc.relation.projectID | 871371 MeM-Scales | es |
dc.relation.projectID | TEC2015-63884-C2-1-P (COGNET) | es |
dc.relation.projectID | G0086 ICON | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9180811 | es |
dc.identifier.doi | 10.1109/ISCAS45731.2020.9180489 | es |
dc.contributor.group | Universidad de Sevilla. TIC178: Diseño y Test de Circuitos Integrados de Señal Mixta | es |
idus.validador.nota | Preprint. Submitted version | es |
dc.eventtitle | 2020 IEEE International Symposium on Circuits and Systems (ISCAS) | es |
dc.eventinstitution | Sevilla (España) | es |