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Mostrando ítems 1-10 de 56
Ponencia
Fast Pipeline 128x128 Pixel Spiking Convolution Core for Event-Driven Vision Processing in FPGAs
(IEEE. Institute of Electrical and Electronics Engineers, 2015)
This paper describes a digital implementation of a parallel and pipelined spiking convolutional neural network (SConvNet) core for processing spikes in an event-driven system. Event-driven vision systems use typically ...
Ponencia
An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links
(IEEE Computer Society, 2014)
Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation ...
Ponencia
On scalable spiking convnet hardware for cortex-like visual sensory processing systems
(IEEE Computer Society, 2010)
This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware using Spiking neural network Address-Event-Representation (AER) technology, for sophisticated pattern and object recognition ...
Ponencia
Experimental Body-input Three-stage DC offset Calibration Scheme for Memristive Crossbar
(IEEE, 2020)
Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are ...
Ponencia
Live Demonstration: Multiplexing AER Asynchronous Channels over LVDS Links with Flow-Control and Clock- Correction for Scalable Neuromorphic Systems
(IEEE Computer Society, 2017)
In this live demonstration we exploit the use of a serial link for fast asynchronous communication in massively parallel processing platforms connected to a DVS for realtime implementation of bio-inspired vision processing ...
Ponencia
LVDS interface for AER links with burst mode operation capability
(IEEE Computer Society, 2008)
This paper presents the design and simulation of a serial AER LVDS communication link. It converts data from classical AER parallel bus with a 4-phase handshaking protocol into a bit stream which is transmitted serially ...
Ponencia
High-Speed Character Recognition System based on a complex hierarchical AER architecture
(IEEE Computer Society, 2008)
In this paper we briefly summarize the fundamental properties of spikes processing applied to artificial vision systems. This sensing and processing technology is capable of very high speed throughput, because it does ...
Artículo
Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits - Application to Voltage-Controlled Ring Oscillators and Frequency-Based sigma Delta ADCs
(Institute of Electrical and Electronics Engineers, 2020)
Abstract— This paper investigates the use of the body terminal of MOS transistors to improve the linearity of some key circuits used to implement analog and mixed-signal circuits integrated in Fully Depleted Silicon on ...
Ponencia
Programmable 2D image filter for AER vision processing
(IEEE Computer Society, 1999)
A VLSI architecture is proposed for the realization of real-time 2D image filtering in an address-event-representation (AER) vision system, The architecture is capable of implementing any convolutional kernel F(x, y) as ...
Ponencia
High-speed image processing with AER-based components
(IEEE Computer Society, 2006)
A high speed sample image processing application using AER-based components is presented. The setup objective is to distinguish between two propellers of different shape rotating at high speed (around 1000 revolutions/sec) ...