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Mostrando ítems 11-20 de 302
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An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links
(IEEE Computer Society, 2014)
Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation ...
Ponencia
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AER tools for Communications and Debugging
(IEEE Computer Society, 2006)
Address-event-representation (AER) is a communications protocol for transferring spikes between bio-inspired chips. Such systems may consist of a hierarchical structure with several chips that transmit spikes among them ...
Ponencia
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On scalable spiking convnet hardware for cortex-like visual sensory processing systems
(IEEE Computer Society, 2010)
This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware using Spiking neural network Address-Event-Representation (AER) technology, for sophisticated pattern and object recognition ...
Ponencia
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Enhanced Parallel Generation of Tree Structures for the Recognition of 3D Images
(Springer, 2019)
Segmentations of a digital object based on a connectivity criterion at n-xel or sub-n-xel level are useful tools in image topological analysis and recognition. Working with cell complex analogous of digital objects, an ...
Ponencia
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AER image filtering
(SPIE Digital LIbrary, 2007-05)
Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows realtime virtual massive connectivity among huge number of neurons located on different chips [1]. By exploiting ...
Ponencia
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FPGA Implementations Comparison of Neuro-cortical Inspired Convolution Processors for Spiking Systems
(Springer, 2009)
Image convolution operations in digital computer systems are usually very expensive operations in terms of resource consumption (processor resources and processing time) for an efficient Real-Time application. In ...
Ponencia
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Experimental Body-input Three-stage DC offset Calibration Scheme for Memristive Crossbar
(IEEE, 2020)
Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are ...
Ponencia
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Live Demonstration: Multiplexing AER Asynchronous Channels over LVDS Links with Flow-Control and Clock- Correction for Scalable Neuromorphic Systems
(IEEE Computer Society, 2017)
In this live demonstration we exploit the use of a serial link for fast asynchronous communication in massively parallel processing platforms connected to a DVS for realtime implementation of bio-inspired vision processing ...
Ponencia
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Universal access to mobile telephony as a way to enhance the autonomy of elderly people
(ACM Digital Library, 2001-05)
The rise of mobile telephony has opened a vast diversity of new opportunities for older people with different levels of physical restrictions due to ageing. Mobile technology allows not only ubiquitous communications but ...
Ponencia
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Virtual Worlds to enhance Ambient-Assisted Living
(IEEE Computer Society, 2010)
In this paper we discuss about the integration of Ambient-Assisted Living (AAL) with virtual worlds. The integration of sensors from the AAL environment (e.g. vital signs, motion sensors) in the Virtual World can enhance ...