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Artículo
Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoC
(MDPI, 2021-01)
The use of deep learning solutions in different disciplines is increasing and their algorithms are computationally expensive in most cases. For this reason, numerous hardware accelerators have appeared to compute their ...
Artículo
A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach
(IEEE Computer Society, 2017)
This paper presents a new architecture, design flow, and field-programmable gate array (FPGA) implementation analysis of a neuromorphic binaural auditory sensor, designed completely in the spike domain. Unlike digital ...
Artículo
A PCI AER Co-Processor Evaluation Based on CPUs Performance Counters
(JIT Editorial Office, Library and Information Center, National Dong Hwa University, 2012)
Image processing in digital computer systems usually considers the visual information as a sequence of frames. These frames are from cameras that capture reality for a short period of time. They are renewed and transmitted ...
Artículo
Stereo Matching in Address-Event-Representation (AER) Bio-Inspired Binocular Systems in a Field-Programmable Gate Array (FPGA)
(MDPI, 2019)
In stereo-vision processing, the image-matching step is essential for results, although it involves a very high computational cost. Moreover, the more information is processed, the more time is spent by the matching ...