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Mostrando ítems 11-20 de 36
Ponencia
Implementation of a time-warping AER mapper
(IEEE Computer Society, 2009)
In recent implementations of neuromorphic spikebased sensors, multi-neuron processors, and actuators; the spike traffic between devices is coded in the form of asynchronous spike streams following the Address-Event-Re ...
Artículo
A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach
(IEEE Computer Society, 2017)
This paper presents a new architecture, design flow, and field-programmable gate array (FPGA) implementation analysis of a neuromorphic binaural auditory sensor, designed completely in the spike domain. Unlike digital ...
Ponencia
Diseño de material específico docente para el aprendizaje de microcontroladores y sistemas USB
(AENUI: Asociación de Enseñantes Universitarios de Informática, 2011)
En la enseñanza en profundidad y especializada en materias de tipo informática nos encontramos con que los contenidos no paran de crecer y cada vez son más difíciles de abarcar. Por otra parte hay que empezar a pensar ...
Tesis Doctoral
Análisis, diseño e implementación de sistemas neuromórficos basados en pulsos para el procesado de información de retinas artificiales
(2011)
Esta tesis se articula en 8 capítulos: Capítulo 1: el presente, dedicado a introducir las motivaciones, los objetivos y la estructura. ... 9;serif'">Capítulo 2: dedicado a repasar algunos de los fundamentos de los sistemas ...
Artículo
Artículo
Low Latency Event-Based Filtering and Feature Extraction for Dynamic Vision Sensors in Real-Time FPGA Applications
(IEEE Computer Society, 2019)
Dynamic Vision Sensor (DVS) pixels produce an asynchronous variable-rate address-event output that represents brightness changes at the pixel. Since these sensors produce frame-free output, they are ideal for real-time ...
Ponencia
Address-Event based Platform for Bio-inspired Spiking Systems
(SPIE Digital LIbrary, 2007-05)
Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows a real-time virtual massive connectivity between huge number neurons, located on different chips. By exploiting ...
Ponencia
Using FPGA for visuo-motor control with a silicon retina and a humanoid robot
(IEEE Computer Society, 2007)
The address-event representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI chips. The event information is transferred using a high speed digital parallel bus. ...
Ponencia
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems
(Neural Information Processing Systems Foundation, 2005)
A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the address-eventrepresentation (AER) is demonstrated. The system includes a retina chip, two convolution chips, a ...
Ponencia
A SpiNNaker Application: Design, Implementation and Validation of SCPGs
(Springer, 2017)
In this paper, we present the numerical results of the implementation of a Spiking Central Pattern Generator (SCPG) on a SpiNNaker board. The SCPG is a network of current-based leaky integrateand- fire (LIF) neurons, ...