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Listar Arquitectura y Tecnología de Computadores por autor "Linares Barranco, Bernabé"
Mostrando ítems 1-20 de 85
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Artículo
A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings
Zamarreño Ramos, Carlos; Kulkarni, Raghavendra; Silva Martínez, José; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 2013)This paper presents a low power fast ON/OFF switchable voltage mode implementation of a driver/receiver pair intended ...
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Artículo
A 32 x 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput
Camuñas Mesa, Luis Alejandro; Acosta Jiménez, Antonio José; Zamarreño Ramos, Carlos; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 2011)This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional ...
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Artículo
A CMOS-memristor hybrid system for implementing stochastic binary spike timing-dependent plasticity
Ahmadi-Farsani, Javad; Ricci, Saverio; Hashemkhani, Shahin; Ielmini, Daniele; Linares Barranco, Bernabé; Serrano Gotarredona, María Teresa (Royal Society Publishing, 2022)This paper describes a fully experimental hybrid system in which a 4 × 4 memristive crossbar spiking neural network (SNN) ...
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Ponencia
A Current Attenuator for Efficient Memristive Crossbars Read-Out
Mohan, Charanraj; Rosa, José M. de la; Vianello, Elisa; Perniola, Luca; Reita, Carlo; Linares Barranco, Bernabé; Serrano Gotarredona, María Teresa (IEEE Computer Society, 2019)This paper presents a new current attenuator circuit to scale down the inference currents in memristor based crossbars that ...
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Ponencia
A General Subthreshold MOS Translinear Theorem
Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé; Andreou, Andreas G. (IEEE Computer Society, 1999)This paper outlines the conditions under which the translinear principle can be fully exploited for MOS transistors operating ...
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Artículo
A Low-Power Current Mode Fuzzy-ART Cell
Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 2006)This paper presents a very large scale integration (VLSI) implementation of a low-power current-mode fuzzy-adaptive ...
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Artículo
A memristive nanoparticle/organic hybrid synapstor for neuro-inspired computing.
Alibart, Fabien; Pleutin, Stéphane; Bichler, Olivier; Gamrat, Christian; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé; Vuillaume, Dominique (Wiley, 2011)A large effort is devoted to the research of new computing paradigms associated with innovative nanotechnologies that ...
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Ponencia
A Methodology for MOS Transistor Mismatch Parameter Extraction and Mismatch Simulation
Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 2000)This paper presents a methodology for mismatch parameter extraction and mismatch simulation using conventional electrical ...
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Ponencia
A Mismatch Calibrated Bipolar Spatial Contrast AER Retina with Adjustable Contrast Threshold
Leñero Bardallo, Juan Antonio; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 2009)Address Event Representation (AER) is an emergent technology for assembling modular multi-blocks bio-inspired sensory ...
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Artículo
A modular current-mode high-precision winner-take-all circuit
Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 1995)In this paper we present a Winner-Take-All (WTA) circuit realized using current-mode circuit design techniques. The ...
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Ponencia
A New Strong Inversion 5-Parameter Transistor Mismatch Model
Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 2000)A new 5-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high ...
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Ponencia
A Physical Interpretation of the Distance Term in Pelgrom’s Mismatch Model results in very Efficient CAD
Linares Barranco, Bernabé; Serrano Gotarredona, María Teresa (IEEE Computer Society, 2007)In 1989 Pelgrom et al. published a mismatch model for MOS transistors, where the standard quadratic deviation of the ...
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Ponencia
A Precise CMOS Mismatch Model for Analog Design from Weak to Strong Inversion
Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé; Velarde Ramírez, Jesús (IEEE Computer Society, 2004)A five parameter mismatch model continuos from weak to strong inversion is presented. The model is an extension of a ...
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Ponencia
A signed spatial contrast event spike retina chip
Leñero Bardallo, Juan Antonio; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 2010)Reported AER (Address Event Representation) contrast retinae perform a contrast computation based on the ratio between a ...
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Artículo
Active Perception with Dynamic Vision Sensors. Minimum Saccades with Optimum Recognition
Yousefzadeh, Amirreza; Orchard, Garrick; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers (IEEE), 2018)Vision processing with Dynamic Vision Sensors (DVS) is becoming increasingly popular. This type of bio-inspired vision ...
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Ponencia
Advanced Vision Processing Systems: Spike-Based Simulation and Processing
Pérez Carrasco, José Antonio; Serrano Gotarredona, María del Carmen; Acha Piñero, Begoña; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (Springer, 2009)In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision ...
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Ponencia
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems
Serrano Gotarredona, Rafael; Oster, M.; Lichtsteiner, P.; Linares Barranco, Alejandro; Paz Vicente, Rafael; Gómez Rodríguez, Francisco de Asís; Kolle Riis, H.; Delbrück, Tobi; Liu, Shih-Chii; Zahnd, S.; Whatley, A.M.; Douglas, R.; Häfliger, P.; Jiménez Moreno, Gabriel; Civit Balcells, Antón; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Bernabé (Neural Information Processing Systems Foundation, 2005)A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the ...
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Ponencia
AER Synthetic Generation in Hardware for Bio-inspired Spiking Systems
Linares Barranco, Alejandro; Linares Barranco, Bernabé; Jiménez Moreno, Gabriel; Civit Balcells, Antón (SPIE Digital Library, 2005-05)Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time ...
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Ponencia
An AER Contrast Retina with On-Chip Calibration
Costas Santos, Jesús; Serrano Gotarredona, María Teresa; Serrano Gotarredona, Rafael; Linares Barranco, Bernabé (IEEE Computer Society, 2007)We present a contrast retina microchip that provides its output as an AER (Address Event Representation) stream. Contrast ...
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Ponencia
An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links
Iakymchuk, T.; Rosado, A.; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé; Jiménez Fernández, Ángel Francisco; Linares Barranco, Alejandro; Jiménez Moreno, Gabriel (IEEE Computer Society, 2014)Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating ...