Presentation
A New Strong Inversion 5-Parameter Transistor Mismatch Model
Author/s | Serrano Gotarredona, María Teresa
![]() ![]() ![]() ![]() ![]() ![]() ![]() Linares Barranco, Bernabé |
Department | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores |
Date | 2000 |
Published in |
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ISBN/ISSN | 0-7803-5482-6 |
Abstract | A new 5-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation strong inversion regions, including short channel transistors. The ... A new 5-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation strong inversion regions, including short channel transistors. The new model is based on splitting the contribution of the mobility degradation parameter mismatch into two components, and modulating them as the transistor transitions from ohmic to saturation regions. The model is tested for a wide range of transistor sizes (30), and shows excellent precision, never reported before for such a wide range of transistor sizes, including short channel transistors. |
Citation | Serrano Gotarredona, M.T. y Linares Barranco, B. (2000). A New Strong Inversion 5-Parameter Transistor Mismatch Model. En ISCAS 2000: IEEE International Symposium on Circuits and Systems (381-384), Geneva, Switzerland: IEEE Computer Society. |
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