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Mostrando ítems 1-9 de 9
Artículo
1 V CMOS subthreshold log domain PDM
(Springer, 2003)
A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing ...
Artículo
Characterization-Based Modeling of Retriggering and Afterpulsing for Passively Quenched CMOS SPADs
(Institute of Electrical and Electronics Engineers, 2019)
The current trend in the design of systems based on CMOS SPADs is to adopt smaller technological nodes, allowing the co-integration of additional electronics for the implementation of complex digital systems on chip. Due ...
Artículo
A detailed study of the gate/drain voltage dependence of RTN in bulk pMOS transistors
(Elsevier, 2019)
Random Telegraph Noise (RTN)has attracted increasing interest in the last years. This phenomenon introduces variability in the electrical properties of transistors, in particular in deeply-scaled CMOS technologies, which ...
Artículo
Low-voltage CMOS log-companding techniques for audio applications
(Springer, 2004)
This paper presents a collection of novel current-mode circuit techniques for the integration of very low-voltage (down to 1 V) low-power (few hundreds of μA) complete SoCs in CMOS technologies. The new design proposal is ...
Artículo
Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS
(Institute of Electrical and Electronics Engineers, 2010)
This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility ...
Artículo
A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process
(MDPI, 2022)
This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution ...
Artículo
A High-voltage Floating Level Shifter for a Multi-stage Charge-pump in a Standard 1.8 V/3.3 V CMOS Process
(Elsevier, 2022)
This paper proposes a high-voltage floating level shifter with a periodically-refreshed charge pump topology. Designed and fabricated in a standard 1.8 V/3.3 V CMOS process, the circuit can withstand shifting voltages from ...
Artículo
Unified RTN and BTI statistical compact modeling from a defect-centric perspective
(Elsevier, 2021-11)
In nowadays deeply scaled CMOS technologies, time-dependent variability effects have become important concerns for analog and digital circuit design. Transistor parameter shifts caused by Bias Temperature Instability and ...
Artículo
Statistical threshold voltage shifts caused by BTI and HCI at nominal and accelerated conditions
(Elsevier, 2021-11)
In nowadays deeply scaled CMOS technologies, time-zero and time-dependent variability effects have become important concerns for analog and digital circuit design. For instance, transistor parameter shifts caused by Bias ...