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Mostrando ítems 31-40 de 364
Artículo
Design considerations for integrated continuous-time chaotic oscillators
(Institute of Electrical and Electronics Engineers, 1998)
This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant ...
Ponencia
A 26.5 nJ/px 2.64 Mpx/s CMOS Vision Sensor for Gaussian Pyramid Extraction
(Institute of Electrical and Electronics Engineers, 2014)
This paper introduces a CMOS vision sensor to extract the Gaussian pyramid with an energy cost of 26.5 nJ/px at 2.64 Mpx/s, thus outperforming conventional solutions employing an imager and a separate digital processor. ...
Ponencia
Modeling OpAmp-induced harmonic distortion for switched-capacitor ΣΔ modulator design
(Institute of Electrical and Electronics Engineers, 1994)
This communication reports a new modeling of opamp-induced harmonic distortion in SC ΣΔ modulators, which is aimed to optimum design of this kind of circuit for high-performance applications. We analyze incomplete transfer ...
Artículo
Switched-Current Chaotic Neurons
(Institution of Engineering and Technology, 1994)
The Letter presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks. They have been fabricated in a double-metal, single-poly 1.6µm CMOS technology. The neuron soma ...
Ponencia
Design of a 1.2-V Cascade Continuous-Time Sigma-Delta Modulator for Broadband Telecommunications
(Institute of Electrical and Electronics Engineers, 2006)
This paper presents the design of a continuous-time multibit cascade 2-2-1 sigma-delta modulator for broadband telecom systems.
Ponencia
Structure reconfigurability of the CNNUC3 for robust template operation
(Institute of Electrical and Electronics Engineers, 2000)
We demonstrate the importance of the reconfigurability of a 64/spl times/64 cells size CNN-UM chip. As we show, in such a high complexity mixed-signal VLSI circuit the switch and internal reference level reconfigurability ...
Ponencia
Architectures and building blocks for CMOS VLSI analog "neural" programmable optimizers
(Institute of Electrical and Electronics Engineers, 1992)
A modular reconfigurable serial architecture is presented for the analog/digital implementation of constrained optimization algorithms with digital programmability of the problem weights. Area overhead due to programmability ...
Artículo
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
(Institute of Electrical and Electronics Engineers, 1997)
This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose ...
Artículo
A Low-Latency, Low-Power CMOS Sun Sensor for Attitude Calculation Using Photovoltaic Regime and On-Chip Centroid Computation
(Institute of Electrical and Electronics Engineers, 2023)
The demand for sun sensors has skyrocketed in the last years due to the huge expected deployment of satellites associated with the New Space concept. Sun sensors compute the position of the sun relative to the observer and ...
Artículo
10mhz cmos ota-c voltage-controlled quadrature oscillator
(Institution of Engineering and Technology, 1989)
A quadrature-type voltage-controlled oscillator with operational transconductance amplifiers and capacitors (OTA-C) is presented. A monolithic integrated CMOS test circuit is introduced to verify theoretical results. The ...