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Mostrando ítems 1-10 de 16
Artículo
Design considerations for integrated continuous-time chaotic oscillators
(Institute of Electrical and Electronics Engineers, 1998)
This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant ...
Ponencia
A multiplexed mixed-signal fuzzy architecture
(Institute of Electrical and Electronics Engineers, 1998)
Analog circuits provide better area/power efficiency than their digital counterparts for low-medium precision requirements. This limit in precision as well as the lack of design tools when compared to the digital approach, ...
Ponencia
Mixed signal CMOS high precision circuits for on chip learning
(Institute of Electrical and Electronics Engineers, 1998)
Learning algorithms have become of great interest to be applied not only to neural or hybrid neuro-fuzzy systems, but also as a tool to achieve a fine tuning of analog circuits, whose main drawback is their lack of precision. ...
Artículo
Multiplexing architecture for mixed-signal CMOS fuzzy controllers
(Institute of Electrical and Electronics Engineers, 1998)
Limited precision imposes limits on the complexity of analogue circuits, and hence fuzzy analogue controllers are usually oriented to fast low-power systems with low-medium complexity. A strategy to preserve most of the ...
Ponencia
Challenges in mixed-signal IC design of CNN chips in submicron CMOS
(Institute of Electrical and Electronics Engineers, 1998)
Summary form only given. The contrast observed between the performance of artificial vision machines and "natural" vision system is due to the inherent parallelism of the former. In particular, the retina combines image ...
Artículo
Sorting networks implemented as νMOS circuits
(Institute of Electrical and Electronics Engineers, 1998)
A new realisation for n-input sorters is presented. Resorting to the neuron-MOS (νMOS) concept and to an adequate electrical scheme, a compact and efficient implementation is obtained.
Ponencia
Four-quadrant one-transistor-synapse for high-density CNN implementations
(Institute of Electrical and Electronics Engineers, 1998)
Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for ...
Artículo
Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors
(Institute of Electrical and Electronics Engineers, 1998)
This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a cascade architecture to obtain high resolution with low oversampling ratio. It is less sensitive to the non-linearity of ...
Ponencia
Practical considerations for the design of cascade multi-bit high-frequency /spl Sigma//spl Delta/ modulators
(Institute of Electrical and Electronics Engineers, 1998)
Recommendations are given for efficient design of high-frequency /spl Sigma//spl Delta/ modulators using multi-stage (cascade) multi-bit quantization architectures. These cover from pure architectural aspects to cell design ...
Artículo
A high-precision current-mode WTA-MAX circuit with multichip capability
(Institute of Electrical and Electronics Engineers, 1998)
This paper presents a circuit design technique suitable for the realization of winner-take-all (WTA), maximum (MAX), looser-take-all (LTA), and minimum (MIN) circuits. The technique presented is based on current replication ...