ListarInstituto de Microelectrónica de Sevilla (IMSE-CNM) por materia "Low power"
Mostrando ítems 1-8 de 8
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Artículo
A Low-Latency, Low-Power CMOS Sun Sensor for Attitude Calculation Using Photovoltaic Regime and On-Chip Centroid Computation
(Institute of Electrical and Electronics Engineers, 2023)The demand for sun sensors has skyrocketed in the last years due to the huge expected deployment of satellites associated ...
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Ponencia
Assessing application areas for tunnel transistor technologies
(Institute of Electrical and Electronics Engineers (IEEE), 2016)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Artículo
Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
(Institute of Electrical and Electronics Engineers, 2016)In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors ...
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Ponencia
Complementary tunnel gate topology to reduce crosstalk effects
(Institute of Electrical and Electronics Engineers (IEEE), 2017)Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome ...
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Ponencia
Exploring logic architectures suitable for TFETs devices
(Institute of Electrical and Electronics Engineers, 2017)Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates ...
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Artículo
Insights Into the Operation of Hyper-FET-Based Circuits
(Institute of Electrical and Electronics Engineers, 2017)Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost ...
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Artículo
Matrix Methods for the Dynamic Range Optimization of Continuous-TimeGm-CFilters
(Institute of Electrical and Electronics Engineers, 2008)This paper presents a synthesis procedure for the optimization of the dynamic range of continuous-time fully differential ...
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Artículo
MOST moderate-weak-inversion region as the optimum design zone for CMOS 2.4-GHz CS-LNAs
(Institute of Electrical and Electronics Engineers, 2014)In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weak-inversion (WI) region is shown to be the optimum ...