Listar Instituto de Microelectrónica de Sevilla (IMSE-CNM) por agencia financiadora "Ministerio de Economía y Competitividad (MINECO). España"
Mostrando ítems 1-20 de 36
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A 515 nW, 0-18 dB programmable gain analog-to-digital converter for in-channel neural recording interfaces
(Institute of Electrical and Electronics Engineers, 2014)This paper presents a low-area low-power Switched-Capacitor (SC)-based Programmable-Gain Analog-to-Digital Converter ...
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A Customizable Thermographic Imaging System for Medical Image Acquisition and Processing
(Institute of Electrical and Electronics Engineers, 2022)A custom system has been developed for medical image acquisition and processing in both the visible and the infrared (IR) ...
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A Low Noise Amplifier for Neural Spike Recording Interfaces
(Multidisciplinary Digital Publishing Institute, 2015)This paper presents a Low Noise Amplifier (LNA) for neural spike recording applications. The proposed topology, based on ...
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A Mobile Platform for Movement Tracking Based on a Fast-Execution-Time Optical-Flow Algorithm
(Institute of Electrical and Electronics Engineers, 2022)A multi-purpose mechanical platform to track moving objects in three-dimensional space has been developed. It is composed ...
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An Event-Driven Classifier for Spiking Neural Networks Fed with Synthetic or Dynamic Vision Sensor Data
(Frontiers Media, 2017)This paper introduces a novel methodology for training an event-driven classifier within a Spiking Neural Network (SNN) ...
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Ponencia
An ultra-low-power voltage-mode asynchronous WTA-LTA circuit
(Institute of Electrical and Electronics Engineers, 2013)This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimummaximum indexing ...
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Ponencia
Assessing application areas for tunnel transistor technologies
(Institute of Electrical and Electronics Engineers (IEEE), 2016)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Ponencia
Boundary cost optimization for Alternate Test
(Institute of Electrical and Electronics Engineers, 2015)Alternate Test has demonstrated in the last decade that advanced machine-learning tools can leverage the accuracy gap ...
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Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators
(Institute of Electrical and Electronics Engineers, 2014)This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed ...
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Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
(Institute of Electrical and Electronics Engineers, 2016)In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors ...
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Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
(Institute of Electrical and Electronics Engineers, 2017)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Compensation of PVT Variations in ToF Imagers with In-Pixel TDC
(MDPI, 2017)The design of a direct time-of-flight complementary metal-oxide-semiconductor (CMOS) image sensor (dToF-CIS) based on a ...
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Ponencia
DOE based high-performance gate-level pipelines
(Institute of Electrical and Electronics Engineers, 2014)Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in ...
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Efficient Hybrid Continuous-Time/Discrete-Time Cascade Modulators for Wideband Applications
(Elsevier, 2014)This paper analyses the use of hybrid continuous-time/discrete-time cascade ΣΔ modulators for the implementation of ...
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Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview
(Wiley-Blackwell, 2017)We provide an overview of selected crypto-hardware devices, with a special reference to the lightweight electronic ...
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Ponencia
Event-driven sensing and processing for high-speed robotic vision
(Institute of Electrical and Electronics Engineers, 2014)We present here an overview of a new vision paradigm where sensors and processors use visual information ...
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Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements
(Institute of Electrical and Electronics Engineers, 2014)Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable ...
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Ponencia
Exploring logic architectures suitable for TFETs devices
(Institute of Electrical and Electronics Engineers, 2017)Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates ...
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FLIP-Q: A QCIF resolution focal-plane array for low-power image processing
(Institute of Electrical and Electronics Engineers, 2011)This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35 CMOS-OPTO process. The chip ...
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Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs
(IEEE, 2021)The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an ...