dc.creator | Mohan, Charanraj | es |
dc.creator | Camuñas Mesa, Luis Alejandro | es |
dc.creator | Rosa, José M. de la | es |
dc.creator | Vianello, Elisa | es |
dc.creator | Serrano Gotarredona, María Teresa | es |
dc.creator | Linares Barranco, Bernabé | es |
dc.date.accessioned | 2021-04-20T11:35:33Z | |
dc.date.available | 2021-04-20T11:35:33Z | |
dc.date.issued | 2021-03 | |
dc.identifier.citation | Mohan, C., Camuñas Mesa, L.A., Rosa, J.M.d.l., Vianello, E., Serrano Gotarredona, M.T. y Linares Barranco, B. (2021). Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration. IEEE Access, 9, 38043-38061. | |
dc.identifier.issn | 2169-3536 | es |
dc.identifier.uri | https://hdl.handle.net/11441/107456 | |
dc.description.abstract | Monolithic integration of silicon with nano-sized Redox-based resistive Random-Access
Memory (ReRAM) devices opened the door to the creation of dense synaptic connections for bio-inspired
neuromorphic circuits. One drawback of OxRAM based neuromorphic systems is the relatively low ON
resistance of OxRAM synapses (in the range of just a few kilo-ohms). This requires relatively large currents
(many micro amperes per synapse), and therefore imposes strong driving capability demands on peripheral
circuitry, limiting scalability and low power operation. After learning, however, a read inference can be
made low-power by applying very small amplitude read pulses, which require much smaller driving currents
per synapse. Here we propose and experimentally demonstrate a technique to reduce the amplitude of read
inference pulses in monolithic neuromorphic CMOS OxRAM-synaptic crossbar systems. Unfortunately,
applying tiny read pulses is non-trivial due to the presence of random DC offset voltages. To overcome
this, we propose nely calibrating DC offset voltages using a bulk-based three-stage on-chip calibration
technique. In this work, we demonstrate spiking pattern recognition using STDP learning on a small 4 4
proof-of-concept memristive crossbar, where on-chip offset calibration is implemented and inference pulse
amplitude could be made as small as 2mV. A chip with pre-synaptic calibrated input neuron drivers and a
4 4 1T1R synapse crossbarwas designed and fabricated in the CEA-LETI MAD200 technology, which uses
monolithic integration of OxRAMs above ST130nm CMOS. Custom-made PCBs hosting the post-synaptic
circuits and control FPGAs were used to test the chip in different experiments, including synapse characterization,
template matching, and pattern recognition using STDP learning, and to demonstrate the use
of on-chip offset-calibrated low-power ampli ers. According to our experiments, the minimum possible
inference pulse amplitude is limited by offset voltage drifts and noise. We conclude the paper with some
suggestions for future work in this direction. | es |
dc.description.sponsorship | International Consortium of Nanotechnologies (ICON) Grant G0086 | es |
dc.description.sponsorship | European Union H2020 grant 824164 (HERMES) | es |
dc.description.sponsorship | European Union H2020 grant 871371 (MeM-Scales) | es |
dc.description.sponsorship | European Union H2020 grant 871501 (NeurONN) | es |
dc.description.sponsorship | European Union H2020 grant 899559 (SpinAge) | es |
dc.description.sponsorship | European Union H2020 grant PCI2019-111826-2 (APPROVIS3D) | es |
dc.description.sponsorship | Spanish Ministry of Science and Innovation Grant PID2019-105556GB-C31 (NANOMIND) | es |
dc.description.sponsorship | Spanish Ministry of Science and Innovation / FEDER Grant PID2019-103876RB-I00 (CORDION) | es |
dc.description.sponsorship | Junta de Andalucía (Spain) Grant US-1260118 (Neuro-Radio) | es |
dc.description.sponsorship | Universidad de Sevilla ( Spain) VI PPIT | es |
dc.format | application/pdf | es |
dc.format.extent | 20 p. | es |
dc.language.iso | eng | es |
dc.publisher | IEEE | es |
dc.relation.ispartof | IEEE Access, 9, 38043-38061. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Neuromorphic | es |
dc.subject | Low-power inference | es |
dc.subject | Pattern recognition | es |
dc.subject | Template matching | es |
dc.subject | Offset calibration | es |
dc.subject | Memristive crossbar | es |
dc.subject | Nano-synapse | es |
dc.title | Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.projectID | (NeurONN) H2020-871501 | es |
dc.relation.projectID | US-1260118 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/9367145 | es |
dc.identifier.doi | 10.1109/ACCESS.2021.3063437 | es |
dc.contributor.group | Universidad de Sevilla. TIC178: Diseño y Test de Circuitos Integrados de Señal Mixta | es |
dc.journaltitle | IEEE Access | es |
dc.publication.volumen | 9 | es |
dc.publication.initialPage | 38043 | es |
dc.publication.endPage | 38061 | es |