dc.creator | Potestad Ordóñez, Francisco Eugenio | es |
dc.creator | Jiménez Fernández, Carlos Jesús | es |
dc.creator | Baena Oliva, María del Carmen | es |
dc.creator | Parra Fernández, María del Pilar | es |
dc.creator | Valencia Barrero, Manuel | es |
dc.date.accessioned | 2021-03-10T08:55:41Z | |
dc.date.available | 2021-03-10T08:55:41Z | |
dc.date.issued | 2018 | |
dc.identifier.citation | Potestad Ordóñez, F.E., Jiménez Fernández, C.J., Baena Oliva, M.d.C., Parra Fernández, M.d.P. y Valencia Barrero, M. (2018). Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. En DCIS 2018: Conference on Design of Circuits and Integrated Circuits Lyon, France: IEEE Computer Society. | |
dc.identifier.isbn | 978-1-7281-0171-2 | es |
dc.identifier.issn | 2640-5563 | es |
dc.identifier.uri | https://hdl.handle.net/11441/105829 | |
dc.description.abstract | The fault injection in ciphers operation is a very
successful mechanism to attack them. The inclusion of elements
of protection against this kind of attacks is more and more
necessary. These mechanisms are usually based on introducing
redundancy, which leads to a greater consumption of resources
or a longer processing time. This article presents how the
introduction of placement restrictions on ciphers can make it
difficult to inject faults by altering the clock signal. It is therefore
a countermeasure that neither increases the consumption of
resources nor the processing time. This mechanism has been
tested on FPGA implementations of the Trivium cipher. Several
tests have been performed on a Spartan 3E device from Xilinx
and the experimental measurements have been carried out with
ChipScope Pro. The tests showed that an adequate floorplanning
is a good countermeasure against these kind of attacks. | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2013-45523-R | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2016-80549-R | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad CSIC 201550E039 | es |
dc.format | application/pdf | es |
dc.format.extent | 6 | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | DCIS 2018: Conference on Design of Circuits and Integrated Circuits (2018). | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Fault Attack | es |
dc.subject | Stream Cipher | es |
dc.subject | Trivium | es |
dc.subject | FPGA | es |
dc.subject | Countermeasure | es |
dc.title | Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | TEC2013-45523-R | es |
dc.relation.projectID | TEC2016-80549-R | es |
dc.relation.projectID | CSIC 201550E039 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/8681467 | es |
dc.identifier.doi | 10.1109/DCIS.2018.8681467 | es |
dc.eventtitle | DCIS 2018: Conference on Design of Circuits and Integrated Circuits | es |
dc.eventinstitution | Lyon, France | es |
dc.relation.publicationplace | New York, USA | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | es |