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dc.creatorPotestad Ordóñez, Francisco Eugenioes
dc.creatorJiménez Fernández, Carlos Jesúses
dc.creatorBaena Oliva, María del Carmenes
dc.creatorParra Fernández, María del Pilares
dc.creatorValencia Barrero, Manueles
dc.date.accessioned2021-03-10T08:55:41Z
dc.date.available2021-03-10T08:55:41Z
dc.date.issued2018
dc.identifier.citationPotestad Ordóñez, F.E., Jiménez Fernández, C.J., Baena Oliva, M.d.C., Parra Fernández, M.d.P. y Valencia Barrero, M. (2018). Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. En DCIS 2018: Conference on Design of Circuits and Integrated Circuits Lyon, France: IEEE Computer Society.
dc.identifier.isbn978-1-7281-0171-2es
dc.identifier.issn2640-5563es
dc.identifier.urihttps://hdl.handle.net/11441/105829
dc.description.abstractThe fault injection in ciphers operation is a very successful mechanism to attack them. The inclusion of elements of protection against this kind of attacks is more and more necessary. These mechanisms are usually based on introducing redundancy, which leads to a greater consumption of resources or a longer processing time. This article presents how the introduction of placement restrictions on ciphers can make it difficult to inject faults by altering the clock signal. It is therefore a countermeasure that neither increases the consumption of resources nor the processing time. This mechanism has been tested on FPGA implementations of the Trivium cipher. Several tests have been performed on a Spartan 3E device from Xilinx and the experimental measurements have been carried out with ChipScope Pro. The tests showed that an adequate floorplanning is a good countermeasure against these kind of attacks.es
dc.description.sponsorshipMinisterio de Economía y Competitividad TEC2013-45523-Res
dc.description.sponsorshipMinisterio de Economía y Competitividad TEC2016-80549-Res
dc.description.sponsorshipMinisterio de Economía y Competitividad CSIC 201550E039es
dc.formatapplication/pdfes
dc.format.extent6es
dc.language.isoenges
dc.publisherIEEE Computer Societyes
dc.relation.ispartofDCIS 2018: Conference on Design of Circuits and Integrated Circuits (2018).
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectFault Attackes
dc.subjectStream Cipheres
dc.subjectTriviumes
dc.subjectFPGAes
dc.subjectCountermeasurees
dc.titleFloorplanning as a practical countermeasure against clock fault attack in Trivium stream cipheres
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Tecnología Electrónicaes
dc.relation.projectIDTEC2013-45523-Res
dc.relation.projectIDTEC2016-80549-Res
dc.relation.projectIDCSIC 201550E039es
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8681467es
dc.identifier.doi10.1109/DCIS.2018.8681467es
dc.eventtitleDCIS 2018: Conference on Design of Circuits and Integrated Circuitses
dc.eventinstitutionLyon, Francees
dc.relation.publicationplaceNew York, USAes
dc.contributor.funderMinisterio de Economía y Competitividad (MINECO). Españaes

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