Programmable kernel analog VLSI convolution chip for real time vision processing

Abstract

A neural architecture that implements a programmable 2D image filter has been presented. The architecture allows to implement any 2D filter F(p,q) decomposable into x-axis and y-axis components F(p,q) = H(p)V(q) such that the product can be approximated by a signed minimum. Positive and negative values of H(p) and V(q) can be programmed. The architecture requires an address even representation (AER) input. This allows to rotate the 2D convolution kernel any angle. Circuit simulation results of critical components were given. System-level behavioral simulations of a 128x128 array have been included which validate the proposed approach.