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dc.creatorMohan, Charanrajes
dc.creatorRosa, José M. de laes
dc.creatorVianello, Elisaes
dc.creatorPerniola, Lucaes
dc.creatorReita, Carloes
dc.creatorLinares Barranco, Bernabées
dc.creatorSerrano Gotarredona, María Teresaes
dc.date.accessioned2020-09-29T10:16:19Z
dc.date.available2020-09-29T10:16:19Z
dc.date.issued2019
dc.identifier.citationMohan, C., Rosa, J.M.d.l., Vianello, E., Perniola, L., Reita, C., Linares Barranco, B. y Serrano Gotarredona, M.T. (2019). A Current Attenuator for Efficient Memristive Crossbars Read-Out. En ISCAS 2019: IEEE International Symposium on Circuits and Systems Sapporo, Japan: IEEE Computer Society.
dc.identifier.isbn978-1-7281-0397-6es
dc.identifier.issn2158-1525es
dc.identifier.urihttps://hdl.handle.net/11441/101569
dc.description.abstractThis paper presents a new current attenuator circuit to scale down the inference currents in memristor based crossbars that drive integrate-and-fire neurons, which subsequently allows to reduce the size of integrating capacitors by several orders of magnitude, making IC integration possible. The proposed circuit uses a linear switch to divide the inference current and scale it down by a factor of about 104. The proposed attenuator has been designed in 130nm CMOS technology. Simulation results considering noise, process and temperature variations are shown to validate the presented approach.es
dc.description.sponsorshipEuropean Union's Horizon 2020 No 687299 NeuRAMes
dc.description.sponsorshipEuropean Union's Horizon 2020 No 824164 HERMESes
dc.formatapplication/pdfes
dc.format.extent5es
dc.language.isoenges
dc.publisherIEEE Computer Societyes
dc.relation.ispartofISCAS 2019: IEEE International Symposium on Circuits and Systems (2019),
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.titleA Current Attenuator for Efficient Memristive Crossbars Read-Outes
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadoreses
dc.relation.projectID687299 NeuRAMes
dc.relation.projectID824164 HERMESes
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8702604es
dc.identifier.doi10.1109/ISCAS.2019.8702604es
dc.eventtitleISCAS 2019: IEEE International Symposium on Circuits and Systemses
dc.eventinstitutionSapporo, Japanes
dc.relation.publicationplaceNew York, USAes
dc.contributor.funderEuropean Union (UE)es
dc.contributor.funderEuropean Union (UE)es

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