Ponencias (Tecnología Electrónica)

URI permanente para esta colecciónhttps://hdl.handle.net/11441/11419

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A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks
(Institute of Electrical and Electronics Engineers, 2023-12) Zúñiga González, Virginia; Tena Sánchez, Erica; Acosta Jiménez, Antonio José; Universidad de Sevilla. Departamento de Tecnología Electrónica; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; European Union’s Horizon 2020 No. 952622; FEDER 2014-2020 and Consejería de Economía, Conocimiento, Empresas y Universidad de la Junta de Andalucía under Project US-1380823; MCIN/AEI/10.13039/501100011033 project Grant PID2020-116664RB-I00; Universidad de Sevilla. TIC180: Diseño de Circuitos Integrados Digitales y Mixtos
As the AES is the standard symmetric cipher selected by NIST, is the best-known and the most widely used block cipher. Consequently, security threats are constantly rising and increasingly powerful. With the addition of the upcoming scenario of quantum computing, these threats have become a front-line concern in the crypto-community. Although is claimed that using larger key sizes in symmetric key algorithms for implementing quantum-resistant implementations is enough to counteract brute force attacks, this paper shows that both AES-128 and AES-256 are vulnerable to Power Analysis attacks. This paper presents a security comparison against Differential Power Analysis (DPA) attacks over both AES 128-256. Through experimental attacks in FPGA AES implementations, results show that although AES-256 reaches a greater level of security than AES-128, is still vulnerable to this kind of attack. Specifically, we have obtained 75% of the bytes needed to find the original key for AES-128 while only 28.125% for AES-256 by performing the same attack.
Aplicación del VHDL en prácticas de diseño de sistemas digitales
(Universidad Politécnica de Madrid, 1994) Acosta Jiménez, Antonio José; Bellido Díaz, Manuel Jesús; Valencia Barrero, Manuel; Barriga Barros, Ángel; Universidad de Sevilla. Departamento de Tecnología Electrónica; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Arquitectura para el diseño de circuitos autotemporizados bidimensionales. Realización de multiplicadores
(Universidad de Málaga, 1993) Acosta Jiménez, Antonio José; Bellido Díaz, Manuel Jesús; Barriga Barros, Ángel; Valencia Barrero, Manuel; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Universidad de Sevilla. Departamento de Tecnología Electrónica; Universidad de Sevilla. TIC180: Diseño de Circuitos Integrados Digitales y Mixtos; Universidad de Sevilla. TIC204: Investigación y Desarrollo Digital
La realización de sistemas digitales mediante técnicas autotemporizadas constituye la mejor alternativa para resolver la problemática de las técnicas síncronas en circuitos VLSI. En esta comunicación se presenta una mejora a la arquitectura autotemporizada presentada en [1,2] y se aplica a la realización de multiplicadores matriciales autotemporizados a nivel de bit.
Asymmetric clock driver for improved power and noise performances
(IEEE Computer Society, 2007) Castro, Javier; Parra Fernández, María del Pilar; Valencia Barrero, Manuel; Acosta Jiménez, Antonio José; Universidad de Sevilla. Departamento de Tecnología Electrónica; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Ministerio de Educación y Ciencia (MEC). España; Junta de Andalucía
One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation and distribution tree. This paper analyzes how the use of an asymmetric clock can be an important solution to reduce the switching noise generated by the global clock, with a very reduced degradation in performances and reliability. The suited sizing of clock generators and the design of asymmetric clock tree cells, show the benefits of the proposed technique, validated through a design example where a 50% of noise reduction is achieved with 10% of loss in operation frequency and no penalty, even saving, in power consumption.
Automated experimental setup for EM cartography to enhance EM attacks
(2022) Tena Sánchez, Erica; Casado Galán, Alejandro; Zúñiga González, Virginia; Potestad Ordóñez, Francisco Eugenio; Acosta Jiménez, Antonio José; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Universidad de Sevilla. Departamento de Tecnología Electrónica; European Union (UE). H2020; Junta de Andalucía; Ministerio de Ciencia e Innovación (MICIN). España
Side-channel attacks are a real threat, exploiting and revealing the secret data stored in our electronic devices just analyzing the leaked information of the cryptographic modules during their normal encryption/decryption operations. In this sense, electromagnetic attacks have been posed as one of the most powerful attacks, retrieving the secret information by analyzing the existing relation between the leaked electromagnetic radiation and the data being processed. These attacks are known as ElectroMagnetic (EM) attacks and a extremely critic point for their success is the EM probe positioning. In this paper, an automated experimental setup for EM cartography is described to enhance EM attacks and to help hardware designers to detect the possible information leakage flaws, as well as to determine the security level reached by the hardware implementations against EM attacks.
Concepción de un microprocesador: de la especificación a la realización
(Universidad Politécnica de Madrid, 2000) Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Acosta Jiménez, Antonio José; Universidad de Sevilla. Departamento de Tecnología Electrónica; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Delay degradation effect in submicronic CMOS inverters
(Université Catholique de Louvain, 1997) Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Barriga Barros, Ángel; Valencia Barrero, Manuel; Universidad de Sevilla. Departamento de Tecnología Electrónica; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Comisión Interministerial de Ciencia y Tecnología (CICYT). España
This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS inverter when consecutive input transition are close in time. Complete understanding of the effect is demonstrated, providing a quantifying model. Fully characterization as a function of design variables and external conditions is carried out, making the model suitable for using in library characterization as well as simulation at a transistor level. Comparison with HSPICE level 6 simulations shows satisfactory accuracy for timing evaluation.
Determinación del coeficiente de resolución en biestables RS CMOS
(Universidad Politécnica de Madrid. Laboratorio de Sistemas Integrados, 1992) Bellido Díaz, Manuel Jesús; Valencia Barrero, Manuel; Acosta Jiménez, Antonio José; Barriga Barros, Ángel; Universidad de Sevilla. Departamento deTecnología Electrónica; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Universidad de Sevilla. TIC204: Investigación y Desarrollo Digital; Universidad de Sevilla. TIC180: Diseño de Circuitos Integrados Digitales y Mixtos
El diseño de biestables con riesgo de metaestabilidad requiere que posean coeficientes de resolución adecuados. En este trabajo, se introducen dos métodos para su medida y se comparan con otro previamente reportado. Uno de nuestros métodos mejora en dos órdenes de magnitud los tiempos de medida.
DPA vulnerability analysis on Trivium stream cipher using an optimized power model
(Institute of Electrical and Electronics Engineers, 2015-07-30) Tena Sánchez, Erica; Acosta Jiménez, Antonio José; Universidad de Sevilla. Departamento de Tecnología Electrónica; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Consejo Superior de Investigaciones Científicas (CSIC); Gobierno de España; Universidad de Sevilla. TIC180: Diseño de Circuitos Integrados Digitales y Mixtos
In this paper, a Differential Power Analysis (DPA) vulnerability analysis on Trivium stream cipher is presented. Compared to the two previously presented DPA attacks on Trivium, we retrieve the whole key without making any hypothesis during the attack. An optimized power model is proposed allowing the power trace acquisition without making any algorithmic-noise removement thus simplifying the attack strategy considerably. The theoretical vulnerability analysis is presented and then checked developing a simulation-based DPA attack on a standard CMOS Trivium implementation in a 90nm TSMC technology. The results show that our attack is successful for random keys, saving in computer resources and time respecting to previously-reported attacks. The attack is independent on technology used for the implementation of Trivium and can be used to measure the security of novel Trivium implementations.
Un entorno informático de ayuda a la docencia de sistemas de comunicación optoelectrónicos
(Universidad Politécnica de Madrid, 2000) Verd, J.; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Universidad de Sevilla. Departamento de Tecnología Electrónica; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Experimental cartography generation methodology for Electromagnetic Fault Injection Attacks [póster]
(IEEE, 2023-11-17) Rincón Beneyto, Juan Carlos; Casado Galán, Alejandro; Potestad Ordóñez, Francisco Eugenio; Acosta Jiménez, Antonio José; Tena Sánchez, Erica; Universidad de Sevilla. Departamento de Tecnología Electrónica; Potestad Ordóñez, Francisco Eugenio; European Union’s Horizon 2020 No.952622; Programa Operativo FEDER 2014- 2020 and Consejería de Economía, Conocimiento, Empresas y Universidad de la Junta de Andalucía under Project US-1380823; MCIN/AEI/10.13039/501100011033 Grant PID2020-116664RB-I00; Universidad de Sevilla. TIC180: Diseño de Circuitos Integrados Digitales y Mixtos
The Electromagnetic Fault Injection (EMFI) is one of the methods to inject faults in the circuits with different purposes, from the security analysis point of view to the study of resilience against environmental conditions of the circuits. Focusing on secure cryptographic applications, in order to study the vulnerability of a circuit and perform successful attacks, it is necessary to induce the electromagnetic (EM) field in a very specific point in the surface of the circuit. This aspect, together with extra inconveniences as for example metal shields of the last metal layers of chips, results in a very poor effi ciency in the fault injection through this technique, hindering the possibilities to perform the attacks. This paper presents a experimental cartography generation methodology to carry out automatic EMFI attacks. The presented methodology allows to improve the efficiency in fault injection attacks, showing the areas where the circuit presents greater vulnerabilities against the EM disturbances, allowing to focus the attacks on those points. As demonstrator vehicle, a SRAM is used. Results show that following the steps of the proposed methodology, it is able to detect the point with the maximum fault injection efficiency, along with a great precision of the fault injection, reaching up to been able to inject one bit single fault in the SRAM.
Gate-Level Simulation of CMOS Circuits Using the IDDM Model
(IEEE Computer Society, 2001) Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel; Universidad de Sevilla. Departamento de Tecnología Electrónica; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Ministerio de Ciencia y Tecnología (MCYT). España
Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is able to take account of the propagation of arbitrarily narrow pulses. As a result, the model is ready to be applied to the simulation and verification of complex circuits. Simulation results show an accuracy similar to HSPICE and greatly improved precision over conventional delay models.
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
(IEEE Computer Society, 2001) Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel; Universidad de Sevilla. Departamento de Tecnología Electrónica; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Ministerio de Ciencia y Tecnología (MCYT). España
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm is intended for including the inertial and degradation delay models. Simulation results are very similar to those obtained by electrical simulators, and show a higher accuracy compared to conventional delay models implemented in current logic simulators.
Hamming-code based fault detection design methodology for block ciphers
(IEEE Computer Society, 2020) Potestad Ordóñez, Francisco Eugenio; Tena Sánchez, Erica; Chaves, Ricardo; Valencia Barrero, Manuel; Acosta Jiménez, Antonio José; Jiménez Fernández, Carlos Jesús; Universidad de Sevilla. Departamento de Tecnología Electrónica; Ministerio de Economía y Competitividad (MINECO). España; European Union (UE)
Fault injection, in particular Differential Fault Analysis (DFA), has become one of the main methods for exploiting vulnerabilities into the block ciphers currently used in a multitude of applications. In order to minimize this type of vulnerabilities, several mechanisms have been proposed to detect this type of attacks. However, these mechanisms can have a significant cost or not adequately cover the implementations against fault attacks. In this paper a novel approach is proposed, consisting in generating the signatures of the internal state using a Hamming code. This allows to cover a larger amount of faults allowing to detect even or odd bit changes, as well as multibit and multi-byte changes, the ones that make ciphers more vulnerable to DFA attacks. As case of study, this approach has been applied to the Advanced Encryption Standard (AES) block cipher implemented on FPGA using T-boxes. The results suggest a higher fault coverage with an overhead of 16% of resource consumption and without any penalty in the frequency degradation.
Inertial and Degradation Delay Model for CMOS Logic Gates
(IEEE Computer Society, 2000) Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel; Universidad de Sevilla. Departamento de Tecnología Electrónica; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial effect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model clearly overcomes the limitations of conventional approaches.
Modeling of Real Bistables in VHDL
(IEEE Computer Society, 1993) Acosta Jiménez, Antonio José; Barriga Barros, Ángel; Valencia Barrero, Manuel; Bellido Díaz, Manuel Jesús; Huertas Díaz, José Luis; Universidad de Sevilla. Departamento de Tecnología Electrónica
A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modelled as a basic structure, orienting its implementation towards its inclusion in a cell library. Two applications are included: description of a more complex latch (D-type) and description of a circuit containing three latches where metastable signals are propagated. Simulation results show that the presented niodel provides very realistic information about the device behavior, which until now had to be obtained through electric simulation.
New CMOS VLSI Linear Self-Timed Architectures
(1995) Acosta Jiménez, Antonio José; Bellido Díaz, Manuel Jesús; Valencia Barrero, Manuel; Barriga Barros, Ángel; Jiménez, R.; Huertas Díaz, José Luis; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
The implementation of digital signal processor circuits via self-timed techniques is currently a valid altemative to solve some problems encountered in synchronous VLSI circuits. However; a main difference between synchronous and asynchronous circuits is the hardware resources needed to implement asynchronous circuits. This communication presents four less-costly alternatives to a previously reported linear selftimed architecture, and their application in the design of FIFO memories. Furthermore, the integration and characterization in the laboratory of prototypes of these FIFOs are presented.
Un nuevo modelo de retraso para puertas lógicas CMOS
(Universidad de Málaga, 1993) Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Núñez, R.; Barriga Barros, Ángel; Valencia Barrero, Manuel; Universidad de Sevilla. Departamento de Tecnología Electrónica; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Universidad de Sevilla. TIC204: Investigación y Desarrollo Digital; Universidad de Sevilla. TIC180: Diseño de Circuitos Integrados Digitales y Mixtos
Los modelos de retraso para puertas lógicas, que usan la mayoría de los simuladores lógicos, carecen de la suficiente precisión. En este trabajo proponemos un nuevo modelo de retraso para las puertas lógicas, que surge directamente del análisis del comportamiento de las mismas. Con este modelo de retraso se obtienen resultados de simulación mucho más próximos a los obtenidos a nivel eléctrico (tipo SPICE) ganando, por tanto, en precisión, mientras mantiene la gran velocidad de los simuladores del nivel lógico temporal.
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters
(Springer, 2002) Parra Fernández, María del Pilar; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel; Universidad de Sevilla. Departamento de Tecnología Electrónica; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Ministerio de Ciencia y Tecnología (MCYT). España
The objective of this paper is to explore the applicability of clock gating techniques to binary counters in order to reduce the power consumption as well as the switching noise generation. A measurement methodology to establish right comparisons between different implementations of gateclocked counters is presented. Basically two ways of applying clock gating are considered: clock gating on independent bits and clock gating on groups of bits. The right selection of bits where clock gating must be applied and the suited composition of groups of bits is essential when applying this technique. We have found groupment of bits is the best option when applying clock gating to reduce power consumption and specially to reduce noise generation.

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Examinando Ponencias (Tecnología Electrónica) por Autor "Acosta Jiménez, Antonio José"